Using FPGA: Difference between revisions

From ArmadeusWiki
mNo edit summary
 
(120 intermediate revisions by 7 users not shown)
Line 1: Line 1:
[[Category: FPGA]]
__NOTOC__
__NOTOC__
== First recommended readings ==
* [[FPGA | FPGA on APF introduction]]


==Developing on the APF FPGA==
==Developing on the APF FPGA==


{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities" width="100%"
{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"


| width="50%" |
| width="50%" |
===Tools===
 
* [[Target_Software_Installation#FPGA_firmware_installation|FPGA firmware installation (on U-Boot)]]
=== FPGA Interfaces ===
* [[ISE WebPack installation on Linux| ISE WebPack (Xilinx's free devt tool) installation]]
 
* [[How_to_make_a_VHDL_design_in_Ubuntu/Debian| How to setup the FPGA toolchain in Ubuntu/Debian]]
* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* [[FPGA_loader | Configure the FPGA from Linux]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* [[FPGA_register | Access the FPGA address domain from Linux]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* [[How to simulate post synthesis and post place & route design with GHDL]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]
 
==== Accessing the FPGA address domain from Linux userspace ====
* [[FPGA_registers_access_from_Linux_userspace_on_APF9328,_APF27_SP,_APF51_SP_and_OPOS6UL_SP | APF9328, APF27_SP, APF51_SP and OPOS6UL_SP]]
* [[FPGA_registers_access_from_Linux_userspace_on_APF6_SP | APF6_SP]]
* [[FPGA_registers_access_from_Linux_userspace_on_OPOS93_SP | OPOS93_SP]]
 
==== Accessing the FPGA address domain from Linux kernel ====
 
* [[FPGA_registers_access_from_Linux_kernel_on_OPOS93_SP | OPOS93_SP]]


| width="50%" |
| width="50%" |


===Xilinx documentation links===
=== FPGA designing on Armadeus platforms ===
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]
 
These examples give the basis to make VHDL design for FPGA.
 
*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
*'''OPOS93_SP'''
** [[OPOS93_SP_FPGA_designing | FPGA designing]]


|----------------
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |
=== Configuring Armadeus platform's FPGA ===
'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]
'''Tools'''
* [[FPGA_loader | FPGA loader Linux driver]]


| width="50%" |
| width="50%" |
===Designs===
* [[Simple blinking LED | LED]]
* [[FPGA and led | Button and LED]]
* [[A simple design with Wishbone bus | Button, Linux drivers, Wishbone bus communication and LED]]


* [[VHDL coding styles]]
=== Design Tools===
* [http://www.xess.com/ho03000.html Nice ideas/examples to look at]
Description of tools used to simulate, to synthesize, and to download/configure FGPA.
 
'''Xilinx'''
* [[ISE WebPack and Vivado]]
 
'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]


| width="50%" |
'''Efinix'''
* [[Efinity]]
 
'''Lattice'''


===Links VHDL===
* [[IceCube | Install IceCube]]
* [http://www.opencores.org www.opencores.org]
* [[Diamond | Install Lattice Diamond]]
* [http://www.chez.com/amouf/syntaxe.htm Syntaxe VHDL (French)]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]
* [http://www.xess.com/ho03000.html Nice ideas/examples to look at]


'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]


|----------------
|----------------
Line 49: Line 84:


| width="50%" |
| width="50%" |
==='''P'''eripheral '''O'''n '''D'''emand ===


* [[POD specification]]
=== Automatize FPGA design making ===
* [https://sourceforge.net/projects/periphondemand/ sources repository]
 
==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.
 
==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions
 
==== CactusII ====
 
[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.


| width="50%" |
| width="50%" |
* [[Specification_feedback|Comments about POD]]
 
=== HDL ===
 
===VHDL ===
 
* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]
 
=== Verilog ===
 
* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification
 
=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====
 
With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.
 
==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.
 
==== [[SpinalHDL]] ====
 
[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.


|----------------
|----------------
Line 62: Line 131:
| width="50%" |
| width="50%" |


===Orchestra===
===Links===
* [[Orchestra | Spécification d'Orchestra (French)]]
Some useful links.
----
 
''Draft:''
''' Wishbone '''
* [[Usecases | Diagrammes des cas d'utilisations du logiciel]]
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf  official Wishbone specifications]
* [[OrchestraPython | Elaboration du projet Orchestra en Python (French)]]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]
* [[FpgaArchitecture | Spécification de l'architecture du FPGA (french)]]
 
''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]
 
''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]
 
''' OpenSource '''
 
* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]


| width="50%" |
| width="50%" |
===Links Wishbone===
 
* [http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf  official Wishbone specifications]
 
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]
|----------------


|}
|}

Latest revision as of 17:31, 9 October 2025


Developing on the APF FPGA

FPGA Interfaces

Accessing the FPGA address domain from Linux userspace

Accessing the FPGA address domain from Linux kernel

FPGA designing on Armadeus platforms

These examples give the basis to make VHDL design for FPGA.

Configuring Armadeus platform's FPGA

Platforms

Tools

Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

Altera

Efinix

Lattice

Microsemi

Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

FuseSoC

FuseSoC is a builder written in Python used to automatize FPGA constructions

CactusII

Graphical IDE for managing FPGA/ASIC design with IPX-ACT standard.

HDL

VHDL

Verilog

  • Verilator an High speed verilog simulator
  • Icarus Famous open-source verilog simulator
  • SymbiYosys open-source Verilog formal verification

Synthesizable Synchronous HDL

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

SpinalHDL

Another HDL generator (VHDL) written in Scala.

Links

Some useful links.

Wishbone

Spartan

CycloneV

OpenSource


Retrieved from "http://wikilegacy.armadeus.com/index.php?title=Using_FPGA&oldid=15268"