OPOS6UL SP Interfaces description
Introduction
This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named EIM for External Interface Module. All description of this bus can be found under the i.MX6UL(L) reference manual in chapter 21 (page 821).
FPGA used on board is an XC6SLX9-2CSG225.
Simplified view
Normal communication between i.MX6UL(L) processor and Spartan6 fpga is done with black following signals :
- EIM_BCLK : Clock
- EIM_DA[15:0]: 16bits data and address bus
- EIM_LBA (ADV): Signal used for data/address muxing
- EIM_RW: Read/Write control signal
- EIM_CS0: Chip select
Gray following signals can be used by EIM (External Interface Memory), but not used in default configuration :
- EIM_EB0: Select byte 0 on bus
- EIM_EB1: Select byte 1 on bus
- OE : Output enable
- EIM_CLK0: second clock (EIM_ACLK)
Blue following signals are used for FPGA configuration from imx. Some EIM (black) signals are also used for it.
- FPGA_INITB: Initialize FPGA
- FPGA_PROGRAM : Program (configure) FPGA
- FPGA_DONE: FPGA configuration is done.
Tutorials
Default configuration on CSx
Clocks
The clock used to clock the FPGA is EIM_BCLK (IO_L1P_CCLK_2(N12) and IO_L29P_GCLK3_2(N8)) and is configured to 99 MHz.
Chip Select
The EIM memory space is mapped into 128 MB total memory space in the processor memory. This memory space begin at address 0x50000000.
| Start address | End address | Size | Name |
|---|---|---|---|
| 0x5000_0000 | 0x57FF_FFFF | 128 MB | EIM (NOR/SRAM) |
The total 128 MB of memory can be divided among the EIM four chip selects. See reference manual of i.MX6ULL for more information.
Timings
Read
- U-Boot: To read one 16 bits value in 0 (0x50000000 in i.MX) do :
BIOS> md.w 50000000 1
- Linux: To read one 16 bits value in 0 (0x50000000 in i.MX) do :
# devmem 0x50000000 16
- Bus timings are following :
Write
- U-Boot: To write one 16 bits value in 0 (0x50000000 in i.MX) do :
BIOS> mw.w 50000000 CAFE
- Linux: To write one 16 bits value in 0 (0x50000000 in i.MX) do :
# devmem 0x50000000 16 0xCAFE
- Bus timings are following :
code & mapping
Pinout
Schematics interfaces is given here :
UCF example for interface generated by POD is given here :
NET "rstgen_syscon00_ext_clk" LOC="N8" | IOSTANDARD=LVCMOS33; # EIM_BCLK NET "rstgen_syscon00_ext_clk" TNM_NET = "rstgen_syscon00_ext_clk"; TIMESPEC "TS_rstgen_syscon00_ext_clk" = PERIOD "rstgen_syscon00_ext_clk" 10.101 ns HIGH 50 %; NET "imx6ul_wb16_wrapper00_imx_da<0>" LOC="P11" | IOSTANDARD=LVCMOS33; # EIM_DA0 NET "imx6ul_wb16_wrapper00_imx_cs_n" LOC="R11" | IOSTANDARD=LVCMOS33; # EIM_CS0 NET "imx6ul_wb16_wrapper00_imx_da<1>" LOC="M11" | IOSTANDARD=LVCMOS33; # EIM_DA1 NET "imx6ul_wb16_wrapper00_imx_da<2>" LOC="N11" | IOSTANDARD=LVCMOS33; # EIM_DA2 NET "imx6ul_wb16_wrapper00_imx_da<10>" LOC="R10" | IOSTANDARD=LVCMOS33; # EIM_DA10 NET "imx6ul_wb16_wrapper00_imx_da<11>" LOC="L9" | IOSTANDARD=LVCMOS33; # EIM_DA11 NET "imx6ul_wb16_wrapper00_imx_da<12>" LOC="M10" | IOSTANDARD=LVCMOS33; # EIM_DA12 NET "imx6ul_wb16_wrapper00_imx_da<13>" LOC="M8" | IOSTANDARD=LVCMOS33; # EIM_DA13 NET "imx6ul_wb16_wrapper00_imx_da<14>" LOC="K8" | IOSTANDARD=LVCMOS33; # EIM_DA14 NET "imx6ul_wb16_wrapper00_imx_da<15>" LOC="L8" | IOSTANDARD=LVCMOS33; # EIM_DA15 NET "imx6ul_wb16_wrapper00_imx_adv" LOC="R7" | IOSTANDARD=LVCMOS33; # EIM_LBA NET "imx6ul_wb16_wrapper00_imx_da<7>" LOC="N6" | IOSTANDARD=LVCMOS33; # EIM_DA7 NET "imx6ul_wb16_wrapper00_imx_rw" LOC="R6" | IOSTANDARD=LVCMOS33; # EIM_RW NET "imx6ul_wb16_wrapper00_imx_da<3>" LOC="P5" | IOSTANDARD=LVCMOS33; # EIM_DA3 NET "imx6ul_wb16_wrapper00_imx_da<4>" LOC="R5" | IOSTANDARD=LVCMOS33; # EIM_DA4 NET "imx6ul_wb16_wrapper00_imx_da<5>" LOC="L6" | IOSTANDARD=LVCMOS33; # EIM_DA5 NET "imx6ul_wb16_wrapper00_imx_da<6>" LOC="L5" | IOSTANDARD=LVCMOS33; # EIM_DA6 NET "imx6ul_wb16_wrapper00_imx_da<8>" LOC="M5" | IOSTANDARD=LVCMOS33; # EIM_DA8 NET "imx6ul_wb16_wrapper00_imx_da<9>" LOC="N5" | IOSTANDARD=LVCMOS33; # EIM_DA9 NET "irq_mngr00_gls_irq" LOC="P3" | IOSTANDARD=LVCMOS33; # FPGA_INITB
APF27 OPOS6UL_SP pin correspondance tables
APF27 | J2 num | OPOS6UL_SP -----------|--------|----------------------- IO_L24P_1 | 22 | IO_L37P_M3DQ0_3 IO_L24N_1 | 23 | IO_L37N_M3DQ1_3 IO_L22P_1 | 24 | IO_L40N_M3DQ7_3 -----------|--------|----------------------- IO_L02N_0 | 26 | IO_L2P_0 IO_L02P_0 | 27 | IO_L2N_0 IO_L04N_0 | 28 | IO_L4P_0 IO_L04P_0 | 29 | IO_L4N_0 IO_L03N_0 | 30 | IO_L6P_0 IO_L03P_0 | 31 | IO_L6N_0 IO_L08N_0 | 32 | IO_L33P_0 IO_L08P_0 | 33 | IO_L33N_0 IO_L10N_0 | 34 | IO_L35P_GCLK17_0 IO_L10P_0 | 35 | IO_L35N_GCLK16_0 IO_L12N_0 | 36 | IO_L37P_GCLK13_0 IO_L12P_0 | 37 | IO_L37N_GCLK12_0 IO_L15N_0 | 38 | IO_L63P_SCP7_0 IO_L15P_0 | 39 | IO_L63N_SCP6_0 IO_L18N_0 | 40 | IO_L65P_SCP3_0 IO_L18P_0 | 41 | IO_L65N_SCP2_0 -----------|--------|----------------------- IO_L24P_3 | 43 | IO_L1P_A25_1 IO_L23P_3 | 44 | IO_L1N_A24_VREF_1 IO_L22N_3 | 45 | IO_L33P_A15_M1A10_1 IO_L20N_3 | 46 | IO_L33N_A14_M1A4_1 IO_L20P_3 | 47 | IO_L37P_A7_M1A0_1 IO_L12P_3 | 48 | IO_L37N_A6_M1A1_1 IO_L15N_3 | 49 | IO_L39P_M1A3_1 IO_L14N_3 | 50 | IO_L39N_M1ODT_1 IO_L11N_3 | 51 | IO_L41P_GCLK9_IRDY1_M1RASN_1 IO_L08N_3 | 52 | IO_L41N_GCLK8_M1CASN_1 IO_L08P_3 | 53 | IO_L43P_GCLK5_M1DQ4_1 IO_L03N_3 | 54 | IO_L43N_GCLK4_M1DQ5_1 IO_L03P_3 | 55 | IO_L45P_A1_M1LDQS_1 IO_L01N_3 | 56 | IO_L45N_A0_M1LDQSN_1 -----------|--------|----------------------- IO_L20N_1 | 99 | IO_L38P_M3DQ2_3 IO_L20P_1 | 98 | IO_L38N_M3DQ3_3 IO_L23N_1 | 97 | IO_L39P_M3LDQS_3 IO_L23P_1 | 96 | IO_L39N_M3LDQSN_3 IO_L22N_1 | 95 | IO_L40P_M3DQ6_3 -----------|--------|----------------------- IO_L01N_0 | 91 | IO_L3P_0 IO_L01P_0 | 90 | IO_L3N_0 IO_L07N_0 | 89 | IO_L5P_0_NOTLX4 IO_L07P_0 | 88 | IO_L5N_0_NOTLX4 IO_L09N_0 | 87 | IO_L7P_0_NOTLX4 IO_L09P_0 | 86 | IO_L7N_0_NOTLX4 IO_L11N_0 | 85 | IO_L34P_GCLK19_0 IO_L11P_0 | 84 | IO_L34N_GCLK18_0 IO_L16N_0 | 83 | IO_L36P_GCLK15_0 IO_L16P_0 | 82 | IO_L36N_GCLK14_0 IO_L17N_0 | 81 | IO_L38P_0_NOTLX4 IO_L17P_0 | 80 | IO_L38N_VREF_0_NOTLX4 IO_L19N_0 | 79 | IO_L40P_0 IO_L19P_0 | 78 | IO_L40N_0 -----------|--------|----------------------- IP_L25N_3 | 75 | IO_L38P_A5_M1CLK_1 IO_L24N_3 | 74 | IO_L38N_A4_M1CLKN_1 IO_L23N_3 | 73 | IO_L40P_GCLK11_M1A5_1 IO_L22P_3 | 72 | IO_L40N_GCLK10_M1A6_1 IO_L12N_3 | 71 | IO_L42P_GCLK7_M1UDM_1 IO_L15P_3 | 70 | IO_L42N_GCLK6_TRDY1_M1LDM_1 IO_L14P_3 | 69 | IO_L44P_A3_M1DQ6_1 IO_L11P_3 | 68 | IO_L44N_A2_M1DQ7_1 IO_L04N_3 | 67 | IO_L46P_FCS_B_M1DQ2_1 IO_L02P_3 | 66 | IO_L46N_FOE_B_M1DQ3_1 IO_L02N_3 | 65 | IO_L47P_FWE_B_M1DQ0_1 IO_L01P_3 | 64 | IO_L47N_LDC_M1DQ1_1 -----------|--------|-----------------------
Simulation model
Some simulation model has been written to test eim in VHDL and in python with cocotb.
VHDL
imx_read and imx_write simulation fonctions are included in POD (Peripheral On Demand) library. Available in platform/opos6ulsp directory.
Cocotb
It's possible to simulate eim access with cocotb module named cocotbext-imxeim.
HDL bus wrapper
Bus wrapper has been written in VHDL and chisel to convert EIM protocol to Wishbone bus protocol.
VHDL
A 16 bits multiplexed EIM to 16bits wishbone master bus is available in POD library. The VHDL sources are available following this link.
Chisel
A chisel package is available in module chisArmadeus to drive Wishbone master bus with EIM bus here.
FPGA Interrupt
To generate an IRQ from the FPGA to the i.MX, the pin FPGA_INITB is used by default. It correspond to GPIO4_IO16 on i.MX.
FPGA J2 connector mapping
Mapping of FPGA pin is given in following csv file.
FPGA configuration protocol
<TODO>
Links
- i.MX6UL(L) reference manual (PDF chapter 21 page 821)
- i.MX6UL(L) Datasheet (PDF)
- Spartan6 configuration (PDF)
- Peripheral On Demand configuration files
