APF6 SP Interfaces description: Difference between revisions
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* [[APF6_SP_The_full_howto | The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]] | * [[APF6_SP_The_full_howto | The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]] | ||
* [[Qsys_USB_BLASTER_Jtag-avalon-MM | Use JTaG USB-Blaster to access avalon bus memory on APF6_SP FPGA]] | |||
= Links = | = Links = | ||
Revision as of 15:28, 23 August 2017
Introduction
This page describe the FPGA interfaces for APF6_SP.
Global schematic of FPGA under APF6_SP
i.MX6 to CycloneV
DDR3 to CycloneV
Pinouts
Howto
- The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O
- Use JTaG USB-Blaster to access avalon bus memory on APF6_SP FPGA
