APF6 SP Interfaces description: Difference between revisions
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This page describe the FPGA interfaces for APF6_SP. | This page describe the FPGA interfaces for APF6_SP. | ||
[[File:CycloneV_APF6_general.png|frame|center|Global schematic of FPGA under APF6_SP]] | |||
= i.MX6 to CycloneV = | = i.MX6 to CycloneV = | ||
* [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]] | * [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]] | ||
* [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]] | * [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]] | ||
* [[APF6_SP_DMA_simple_howto | APF6_SP_DMA_simple_howto]] | |||
= Pinouts = | = Pinouts = | ||
* [[APF6_SP hirose pinout | Pinout on apf6sp hirose connector]] | * [[APF6_SP hirose pinout | Pinout on apf6sp hirose connector]] | ||
* [[APF6_SP CycloneV pinout | All pinout for PCIe, DDR3, ...]] | |||
= Howto = | = Howto = | ||
* [[APF6_SP_The_full_howto | The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]] | * [[APF6_SP_The_full_howto | The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]] | ||
* [[Qsys_USB_BLASTER_Jtag-avalon-MM | Use JTaG USB-Blaster to access avalon bus memory on APF6_SP FPGA]] | |||
= Links = | = Links = | ||
* [[Pci debug]]: a tool for read/write in PCIe BAR. | |||
Latest revision as of 12:42, 5 July 2021
Introduction
This page describe the FPGA interfaces for APF6_SP.
Global schematic of FPGA under APF6_SP
i.MX6 to CycloneV
- IMX6-CycloneV interface description (PCIe)
- DDR3-CycloneV interface description
- APF6_SP_DMA_simple_howto
Pinouts
Howto
- The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O
- Use JTaG USB-Blaster to access avalon bus memory on APF6_SP FPGA
Links
- Pci debug: a tool for read/write in PCIe BAR.
