OPOS6UL SP Interfaces description: Difference between revisions

From ArmadeusWiki
 
No edit summary
Line 1: Line 1:
[[Using_FPGA| << FPGA general page]]
[[Category: OPOS6UL_SP]]
[[Category: OPOS6UL_SP]]
[[Category: FPGA]]
[[Category: FPGA]]
Line 5: Line 4:
[[Category: ISE]]
[[Category: ISE]]
[[Category: XILINX]]
[[Category: XILINX]]
{{Under Construction}}
== Introduction ==
This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule.
== Links ==
* [https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf i.MX6UL(L) reference manual](PDF chapter 21 page 821)
[[Using_FPGA| << FPGA general page]]

Revision as of 08:48, 12 September 2018


Page under construction... Construction.png Informations on this page are not guaranteed !!

Introduction

This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named EIM for External Interface Module.


Links

<< FPGA general page