OPOS93 SP Interfaces description
Introduction
The Trion T20 FPGA is accessed by the iMX93 SoC by using a custom FlexIO bus called FlexIO Armabus.
FlexIO Armabus
The FlexIO Armabus is using FlexIO lines to design a custom 8b parallel communication bus. It consists of the following signals:
- clk: Clock of the bus. Data is shifted out on rising edge and latched on falling edge.
- add_select: Address select, next byte is an address byte.
- data_select: Data select, next byte is a data byte.
- write_enable: Write enable, 1 to write, 0 to read.
- data: Bi-directionnal 8b data.
The memory space mapped on the bus is 16 bits wide. Read/write access are done on 32b (hence 4x 8b transfer).
Read example
The following picture depicts a 32 bits read of the word 0xCAFEBABE at address 0x0042.
Write example
The following picture depicts a 32 bits write of the word 0xDEADBEEF at address 0x1545.
Address auto-increment mode
Address is automatically incremented after each fourth byte transferred. The following chronogram depicts a write of the words 0xDEADBEEF, 0xCAFEBABE, 0xFEEDBEBE at 0x0102, 0x0103, 0x0104 respectively.
Burst mode
Burst mode allow a much faster read than standard read mode by anticipating the data to set on the FlexIO Armabus lines. To initiate a burst read, the add_select and the data_select signal should be set at the same time. The write_enable signal should be set too during the first 2 transactions in order to write the size to read. Then, the write_enable should be low until the end of the transfer. Finally, the data are provided on the bus. Please note that the number of clock cycles during the read phase must match the size set earlier.
The following chronogram depicts a burst read of 3 32-bits words at address 0x0023.
