OPOSA5E SP Interface description

Introduction

The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone.

Bridges HPS-FPGA

Interfaces

There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5

• FPGA-to-HPS (F2H) : 256b ACE5-Lite
• HPS-to-FPGA (H2F) : 32/64/128 bits AXI4 interface
• Lightweight HPS-to-FPGA (LWH2F) : 32 bits AXI4 interface
• FPGA-to-SDRAM (F2SDRAM) : 256b/128b/64b AXI-4

The full documentation is available on Altera website

2 bridges can be directly used from HPS to read/write access :

Bridge address

Bridge	Offset	size
HPS-to-FPGA (H2F)	00_4000_0000	1 GB
Lightweight HPS-to-FPGA (LWH2F)	00_2000_0000	512 MB

Bridge must be activated before use with `bridge` command in U-Boot :

OPOSA5E_SP # bridge -h
bridge - SoCFPGA HPS FPGA bridge control

Usage:
bridge enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges 
bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10
For example:
1) To enable and disable all bridges (command without mask):
	a) bridge enable
	b) bridge disable
2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask):
	a) bridge enable 0x3
	b) bridge disable 0x3

For example, to activate the LWH2F bridge do :

OPOSA5E_SP # bridge enable 0x2

Accesses can be done in U-Boot with `md.l` and `mw.l` commands:

OPOSA5E_SP # md.l 0x20010060 1  
20010060: 0000000e                             ....

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