OPOSA5E SP Interface description: Difference between revisions
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== Introduction == | == Introduction == | ||
The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone. | |||
[[File:oposa5e_sp_agilex5_bridges.jpg|Bridges HPS-FPGA|center]] | |||
== Interfaces == | |||
There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5 | There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5 | ||
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The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website] | The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website] | ||
Bridge must be activated before use : | |||
* With `bridge` command in uboot : | |||
<pre class="apf"> | |||
OPOSA5E_SP # bridge -h | |||
bridge - SoCFPGA HPS FPGA bridge control | |||
Usage: | |||
bridge enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges | |||
bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges | |||
Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10 | |||
For example: | |||
1) To enable and disable all bridges (command without mask): | |||
a) bridge enable | |||
b) bridge disable | |||
2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask): | |||
a) bridge enable 0x3 | |||
b) bridge disable 0x3 | |||
</pre> | |||
For example, to activate the LWH2F bridge do : | |||
<pre class="apf"> | |||
OPOSA5E_SP # bridge enable 0x2 | |||
</pre> | |||
[[Using_FPGA| << FPGA general page]] | [[Using_FPGA| << FPGA general page]] | ||
Revision as of 09:52, 30 October 2026
Introduction
The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone.
Interfaces
There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5
- FPGA-to-HPS (F2H) bridge
- HPS-to-FPGA (H2F) bridge
- Lightweight HPS-to-FPGA (LWH2F) bridge
- FPGA-to-SDRAM (F2SDRAM) bridge
The full documentation is available on Altera website
Bridge must be activated before use :
- With `bridge` command in uboot :
OPOSA5E_SP # bridge -h bridge - SoCFPGA HPS FPGA bridge control Usage: bridge enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10 For example: 1) To enable and disable all bridges (command without mask): a) bridge enable b) bridge disable 2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask): a) bridge enable 0x3 b) bridge disable 0x3
For example, to activate the LWH2F bridge do :
OPOSA5E_SP # bridge enable 0x2
