OPOSA5E SP Interface description: Difference between revisions
From ArmadeusWiki
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[[Category: Agilex5]] | [[Category: Agilex5]] | ||
[[Category: FPGA]] | [[Category: FPGA]] | ||
== Introduction == | == Introduction == | ||
[[File:oposa5e_sp_agilex5_bridges.jpg|caption]] | |||
There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5 | |||
* FPGA-to-HPS (F2H) bridge | |||
* HPS-to-FPGA (H2F) bridge | |||
* Lightweight HPS-to-FPGA (LWH2F) bridge | |||
* FPGA-to-SDRAM (F2SDRAM) bridge | |||
The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website] | |||
[[Using_FPGA| << FPGA general page]] | [[Using_FPGA| << FPGA general page]] | ||
Revision as of 09:23, 30 October 2026
Introduction
There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5
- FPGA-to-HPS (F2H) bridge
- HPS-to-FPGA (H2F) bridge
- Lightweight HPS-to-FPGA (LWH2F) bridge
- FPGA-to-SDRAM (F2SDRAM) bridge
The full documentation is available on Altera website
