OPOS93 SP FPGA designing

Requisites

You'll need to install Efinity in order to synthetise your design for the embedded Efinix Trion T20.

Starting from a template project

Template projects for Chisel or Verilog/VHDL development are publicly available on the flexIO to Wishbone bus wrapper repository.

Chisel

1. Install Scala/SBT on your environment
2. Setup a Chisel project and add the flexIO to Wishbone bus wrapper as a dependency
3. From the flexIO to Wishbone bus wrapper repository, copy the opos93sp-template or opos93sp-template-wb (with Wishbone bus instantiated) folder from the hardware directory.
4. You can then hack the different files:
   • Makefile: change your project name, change your Chisel project's directory, ...
   • generate-project.py: IO configurations of the FPGA (see documentation from Efinix)
5. Load Efinity's environment variables (do it only one time):

   $ source <EFINITY_PATH>/bin/setup.sh

6. Build the project

    $ make 

Verilog/VHDL

The flexIO to Wishbone bus wrapper repository build template projects for every releases. Those tamplate projects can be found under the asset section on the release page.

1. Download the Opos93SP template project or the Opos93SP wishbone template project whether you need a Wishbone bus or not.
2. Open the project in Efinity and start hacking the generated wishbone or FlexIO Verilog modules depending on the template project you chose in the step above.

JTAG Debugging

JTAG debugging using Efinity can be achieved following this procedure:

1. Synthetise the design (only the Synthetise step is required)
2. Generate a debug core using the "Debug Wizard" of Efinity
3. Add the signals you are interested in
4. Generate the bitstream (you can skip the Synthesis' step and resume from the Mapping step)
5. Configure the FPGA with the generated bitstream
6. Open the Efinity debugger and attach the target

Now you should be able to trigger acquisition, see instant signal values, etc ...