POD roadmap: Difference between revisions
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* POD 2.0 : | * POD 2.0 : | ||
** Adding Verilog | ** Adding Verilog HDL language | ||
** Generate SystemC testbench | ** Generate SystemC testbench | ||
** Manage Verilog to SystemC conversion (with verilator) for testbench | ** Manage Verilog to SystemC conversion (with verilator) for testbench | ||
Revision as of 10:58, 2 August 2011
This is the roadmap of POD :
- POD 1.0 :
- VHDL Intercon generation
- VHDL top generation
- ARMadeus 4.0 templates available for multiple instances of a component
- POD 1.1 :
- platform and library out of POD repository (?)
- Manage FPGA IOs settings with FPGA configuration files for each type of FPGA.
- POD 2.0 :
- Adding Verilog HDL language
- Generate SystemC testbench
- Manage Verilog to SystemC conversion (with verilator) for testbench
