OPOSA5E SP Interface description: Difference between revisions
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There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5 | There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5 | ||
* FPGA-to-HPS (F2H) | * FPGA-to-HPS (F2H) : 256b ACE5-Lite | ||
* HPS-to-FPGA (H2F) | * HPS-to-FPGA (H2F) : 32/64/128 bits AXI4 interface | ||
* Lightweight HPS-to-FPGA (LWH2F) | * Lightweight HPS-to-FPGA (LWH2F) : 32 bits AXI4 interface | ||
* FPGA-to-SDRAM (F2SDRAM) | * FPGA-to-SDRAM (F2SDRAM) : 256b/128b/64b AXI-4 | ||
The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website] | The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website] | ||
2 bridges can be directly used from HPS to read/write access : | |||
{| class="wikitable" style="margin:auto" | |||
|+ Bridge address | |||
|- | |||
! Bridge !! Offset !! size | |||
|- | |||
| HPS-to-FPGA (H2F) || 00_4000_0000 || 1 GB | |||
|- | |||
| Lightweight HPS-to-FPGA (LWH2F) || 00_2000_0000 ||512 MB | |||
|} | |||
Bridge must be activated before use with `bridge` command in [https://u-boot-project.org/ U-Boot] : | |||
<pre class="apf"> | <pre class="apf"> | ||
OPOSA5E_SP # bridge -h | OPOSA5E_SP # bridge -h | ||
| Line 49: | Line 59: | ||
<pre class="apf"> | <pre class="apf"> | ||
OPOSA5E_SP # bridge enable 0x2 | OPOSA5E_SP # bridge enable 0x2 | ||
</pre> | |||
Accesses can be done in U-Boot with `md.l` and `mw.l` commands: | |||
<pre class="apf"> | |||
OPOSA5E_SP # md.l 0x20010060 1 | |||
20010060: 0000000e .... | |||
</pre> | </pre> | ||
[[Using_FPGA| << FPGA general page]] | [[Using_FPGA| << FPGA general page]] | ||
Latest revision as of 10:10, 30 October 2026
Introduction
The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone.
Interfaces
There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5
- FPGA-to-HPS (F2H) : 256b ACE5-Lite
- HPS-to-FPGA (H2F) : 32/64/128 bits AXI4 interface
- Lightweight HPS-to-FPGA (LWH2F) : 32 bits AXI4 interface
- FPGA-to-SDRAM (F2SDRAM) : 256b/128b/64b AXI-4
The full documentation is available on Altera website
2 bridges can be directly used from HPS to read/write access :
| Bridge | Offset | size |
|---|---|---|
| HPS-to-FPGA (H2F) | 00_4000_0000 | 1 GB |
| Lightweight HPS-to-FPGA (LWH2F) | 00_2000_0000 | 512 MB |
Bridge must be activated before use with `bridge` command in U-Boot :
OPOSA5E_SP # bridge -h bridge - SoCFPGA HPS FPGA bridge control Usage: bridge enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10 For example: 1) To enable and disable all bridges (command without mask): a) bridge enable b) bridge disable 2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask): a) bridge enable 0x3 b) bridge disable 0x3
For example, to activate the LWH2F bridge do :
OPOSA5E_SP # bridge enable 0x2
Accesses can be done in U-Boot with `md.l` and `mw.l` commands:
OPOSA5E_SP # md.l 0x20010060 1 20010060: 0000000e ....
