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| == Introduction ==
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| On APF6_SP it's possible to use the PCI express bus to configure fpga (cycloneV). This article describe how to do that.
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| == Generate files ==
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| === Quartus configuration ===
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| Your design must include the PCIe and CvP components. Once the project synthesized, open the menu
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| <pre class="config">
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| File -> Convert Programming Files ...
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| </pre>
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| * In '''Output programming file''' select the '''programming file type:''' Raw Binary File (.rbf).
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| * In '''Input files to convert''' clic on '''Add Files...''' and add your binary.sof file.
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| * In '''Output programming file''' check the option Create CvP files (Generate binary.periph.rbf and binary.core.rbf)
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| * Click on '''Generate'''
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| You will get two files :
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| * '''binary.periph.rbf''': peripheral config file to be loaded via serial config bus with uboot
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| * '''binary.core.rbf''': core config file to be loaded via PCIe bus with Linux.
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| === Linux configuration ===
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| == Configure the FPGA ==
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| === Peripheral configuration in uboot ===
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| PCIe must be activated before Linux boot. To do that, just load the peripheral bitstream with uboot :
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| <pre class="apf">
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| BIOS> tftpboot ${loadaddr} 192.168.0.117:binary.periph.rbf
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| BIOS> fpga load 0 ${loadaddr} ${filesize}
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| </pre>
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| Then boot Linux:
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| <pre class="apf">
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| BIOS> boot
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| </pre>
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| === Core configuration in Linux ===
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| == Links ==
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