IMX27-Spartan3A interface description: Difference between revisions

Revision as of 16:57, 12 January 2012

This article describe the bus interface configuration to communicate between i.MX27 processor and Spartan3A FPGA.

figure 1 - i.MX27-Spartan3A bus description

Revision as of 16:55, 12 January 2012 (view source) FabienM (talk \| contribs) (New page: 700px\|center\|thumb\|'''figure 1''' - ''i.MX27-Spartan3A bus description'')		Revision as of 16:57, 12 January 2012 (view source) FabienM (talk \| contribs) No edit summary Newer edit →
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			This article describe the bus interface configuration to communicate between i.MX27 processor and Spartan3A FPGA.

	[[image:Imx27-spartan3A.jpg\|700px\|center\|thumb\|'''figure 1''' - ''i.MX27-Spartan3A bus description'']]		[[image:Imx27-spartan3A.jpg\|700px\|center\|thumb\|'''figure 1''' - ''i.MX27-Spartan3A bus description'']]