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| The SP_Vision board is an extension of [[APF27Dev]] and [[APF51Dev]] with a Spartan6 and two DDR. It is designed for real-time video processing. | | The SP_Vision board is an extension of [[APF27Dev]] and [[APF51Dev]] with a Spartan6 and two DDR. It is designed for real-time video processing. |
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| == Configure the Spartan6 with apf27-Dev== | | == Configure the sp_vision Spartan6 with apf27-Dev == |
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| Spartan6 selectmap configuration port is plugged on generic IO of [[APF27]] Spartan3 FPGA. Then, to configure Spartan6, a specific virtual component is required under Spartan3. | | == Configure the sp_vision Spartan6 with apf51-Dev == |
| This virtual component is available under POD components library and is named ''spartan_selectmap''. This component must be added to your Spartan3 design to enable SP_vision Spartan6 configuration.
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| A simple Spartan3 design is available under ARMadeus project tree ''firmware/sp_vision_config/'' to simplify sp_vision config. The design can be synthetized with ISE using the TCL script ''firmware/sp_vision_config/synthesis/testconfig.tcl''.
| | '''TODO''' |
| The already synthetized bitstream is also available under ''firmware/sp_vision_config/bitstream/''.
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| Then to configure Spartan6 :
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| * first configure [[APF27]]'s Spartan3:
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| <pre class="apf">
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| BIOS> tftpboot ${loadaddr} top_testconfig.bit
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| BIOS> fpga load 0 ${loadaddr} 2486f
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| </pre>
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| * then configure the second FPGA using ''loadsecond'' operator:
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| <pre class="apf">
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| BIOS> tftpboot ${loadaddr} spartan6_example_top.bit
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| BIOS> fpga loadsecond 1 ${loadaddr} 16a674 D6000000 1
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| </pre>
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Revision as of 18:26, 27 September 2011
Page under construction...
Informations on this page are not guaranteed !!
Introduction
The SP_Vision board is an extension of APF27Dev and APF51Dev with a Spartan6 and two DDR. It is designed for real-time video processing.
Configure the sp_vision Spartan6 with apf27-Dev
Configure the sp_vision Spartan6 with apf51-Dev
TODO
Informations on this page are not guaranteed !!
