Simple blinking LED - Revision history

FabienM: /* Quartus */

2021-11-25T13:24:02Z

Quartus

← Older revision		Revision as of 15:24, 25 November 2021
Line 106:		Line 106:
	=== Quartus ===		=== Quartus ===

	Se the [[Quartus]] page for tutorials.		See the [[Quartus]] page for tutorials.

	== Configure FPGA ==		== Configure FPGA ==

FabienM: /* Quartus */

2021-11-05T12:57:33Z

Quartus

← Older revision		Revision as of 14:57, 5 November 2021
Line 106:		Line 106:
	=== Quartus ===		=== Quartus ===

	Se the [[Quartus]] page for ~~installation~~ tutorials.		Se the [[Quartus]] page for tutorials.

	== Configure FPGA ==		== Configure FPGA ==

FabienM: /* Quartus */

2021-11-05T12:56:52Z

Quartus

← Older revision		Revision as of 14:56, 5 November 2021
Line 106:		Line 106:
	=== Quartus ===		=== Quartus ===

	~~{{Under_Construction}}~~		Se the [[Quartus]] page for installation tutorials.

	== Configure FPGA ==		== Configure FPGA ==

FabienM: /* VHDL code */ invert reset

2015-02-18T13:17:18Z

VHDL code: invert reset

← Older revision		Revision as of 15:17, 18 February 2015
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	architecture RTL of led is		architecture RTL of led is
	constant max_count : natural := 48000000;		constant max_count : natural := 48000000;
	signal ~~Rst_n~~ : std_logic;		signal Rst : std_logic;
	begin		begin

	~~Rst_n~~ <= '1';		Rst <= '0';

	-- 0 to max_count counter		-- 0 to max_count counter
	compteur : process(refclk, ~~Rst_n~~)		compteur : process(refclk, Rst)
	variable count : natural range 0 to max_count;		variable count : natural range 0 to max_count;
	begin		begin
	if ~~Rst_n~~ = '0' then		if Rst = '1' then
	count := 0;		count := 0;
	led <= '1';		led <= '1';

FabienM: /* VHDL code */

2015-02-17T09:46:08Z

VHDL code

← Older revision		Revision as of 11:46, 17 February 2015
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	architecture RTL of led is		architecture RTL of led is
	constant max_count : natural := 48000000;		constant max_count : natural := 48000000;
			signal Rst_n : std_logic;
	begin		begin

FabienM at 09:44, 17 February 2015

2015-02-17T09:44:51Z

← Older revision		Revision as of 11:44, 17 February 2015
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	use IEEE.numeric_std.all;		use IEEE.numeric_std.all;

	entity ~~Clk_div_led~~ is		entity led is
	Port (		Port (
	~~Clk~~ : in std_logic;		refclk : in std_logic;
	led : out std_logic		led : out std_logic
	);		);
	end ~~Clk_div_led~~;		end led;

	architecture RTL of ~~Clk_div_led~~ is		architecture RTL of led is
	constant max_count : natural := 48000000;		constant max_count : natural := 48000000;
	~~signal Rst_n : std_logic;~~
	begin		begin

	Rst_n <= '1';		Rst_n <= '1';
	~~led <= '0';~~

	-- 0 to max_count counter		-- 0 to max_count counter
	compteur : process(~~Clk~~, Rst_n)		compteur : process(refclk, Rst_n)
	variable count : natural range 0 to max_count;		variable count : natural range 0 to max_count;
	begin		begin
	if Rst_n = '0' then		if Rst_n = '0' then
	count := 0;		count := 0;
	elsif rising_edge(~~Clk~~) then		led <= '1';
			elsif rising_edge(refclk) then
	if count < max_count/2 then		if count < max_count/2 then
	count := count + 1;		count := count + 1;
			led <= '1';
	elsif count < max_count then		elsif count < max_count then
			led <= '0';
	count := count + 1;		count := count + 1;
	else		else
			led <= '1';
	count := 0;		count := 0;
	end if;		end if;
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	=== Pinout ===		=== Pinout ===
			To synthesize this code, use [[ISE_WebPack_installation_on_Linux \| Xilinx Web Pack]], create a new project and add this VHDL module.

	~~To synthesize this code, create a new project and add this VHDL module.~~		{{Note\| Don't forget to power the FPGA IO bank as explained in [[datasheet]]}}

	{{Note\| ~~For '''APF27''' and '''APF51''' don~~'t forget to power the FPGA IO bank as explained in [[datasheet]]}}

	ISE/Quartus need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.		ISE/Quartus need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.

FabienM: /* VHDL code */

2015-02-16T13:08:15Z

VHDL code

← Older revision		Revision as of 15:08, 16 February 2015
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	Port (		Port (
	Clk : in std_logic;		Clk : in std_logic;
	led : out std_logic;		led : out std_logic
	);		);
	end Clk_div_led;		end Clk_div_led;
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	end RTL;		end RTL;
	</source>		</source>

	=== Pinout ===		=== Pinout ===

FabienM: /* Pinout */

2015-02-16T09:04:54Z

Pinout

← Older revision		Revision as of 11:04, 16 February 2015
Line 49:		Line 49:
	To synthesize this code, create a new project and add this VHDL module.		To synthesize this code, create a new project and add this VHDL module.

	{{Note\| For '''APF27''' don't forget to power the FPGA IO bank as explained in [[datasheet]]}}		{{Note\| For '''APF27''' and '''APF51''' don't forget to power the FPGA IO bank as explained in [[datasheet]]}}

	ISE/Quartus need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.		ISE/Quartus need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.

FabienM: /* Pinout */

2015-02-16T09:04:26Z

Pinout

← Older revision		Revision as of 11:04, 16 February 2015
Line 46:		Line 46:
	</source>		</source>
	=== Pinout ===		=== Pinout ===
	~~To synthesize this code, use [[ISE_WebPack_installation_on_Linux \| Xilinx Web Pack]], create a new project and add this VHDL module.~~

	{{Note\| ~~Don~~'t forget to power the FPGA IO bank as explained in [[datasheet]]}}		To synthesize this code, create a new project and add this VHDL module.

			{{Note\| For '''APF27''' don't forget to power the FPGA IO bank as explained in [[datasheet]]}}

	ISE/Quartus need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.		ISE/Quartus need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.

FabienM at 09:03, 16 February 2015

2015-02-16T09:03:16Z

← Older revision		Revision as of 11:03, 16 February 2015
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	[[Category: FPGA]]		[[Category: FPGA]]
	This design introduce FPGA usage on APF. The design will allow you to synthesize a design and configure the FGPA to blink a LED.		This design introduce FPGA usage on APF. The design will allow you to synthesize a design and configure the FGPA to blink a LED.

	~~{{Note\|~~
	~~For APF9328_devlight you will have to connect a LED as described on figure 1.~~
	~~[[image:diode.png\|center\|frame\|'''figure 1''' - ''LED wiring for APF9328 devlight'']]~~
	~~On all others DevBoard, a led is already soldered on FPGA}}~~


	== The design ==		== The design ==
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	entity Clk_div_led is		entity Clk_div_led is
	Port (		Port (
	Clk : in std_logic;		Clk : in std_logic;
	~~led_cathode~~ : out std_logic;		led : out std_logic;
	~~led_anode : out std_logic~~
	);		);
	end Clk_div_led;		end Clk_div_led;
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	Rst_n <= '1';		Rst_n <= '1';
	~~led_cathode~~ <= '0';		led <= '0';

	-- 0 to max_count counter		-- 0 to max_count counter
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	if Rst_n = '0' then		if Rst_n = '0' then
	count := 0;		count := 0;
	~~led_anode <= '1';~~
	elsif rising_edge(Clk) then		elsif rising_edge(Clk) then
	if count < max_count/2 then		if count < max_count/2 then
	~~led_anode <='1';~~
	count := count + 1;		count := count + 1;
	elsif count < max_count then		elsif count < max_count then
	~~led_anode <='0';~~
	count := count + 1;		count := count + 1;
	else		else
	count := 0;		count := 0;
	~~led_anode <='1';~~
	end if;		end if;
	end if;		end if;
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	{{Note\| Don't forget to power the FPGA IO bank as explained in [[datasheet]]}}		{{Note\| Don't forget to power the FPGA IO bank as explained in [[datasheet]]}}

	ISE need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.		ISE/Quartus need to know where to branch LED pins on its IO, this pinout is describe in constraint file with extension '''.ucf'''.

	* For '''APF9328''':		* For '''APF9328''':
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	TIMESPEC "TS_Clk" = PERIOD "Clk" 10.42 ns HIGH 50 %;		TIMESPEC "TS_Clk" = PERIOD "Clk" 10.42 ns HIGH 50 %;
	# LED		# LED
	NET "~~led_cathode~~" LOC = "P118~~"\| IOSTANDARD = LVCMOS33 ;~~		NET "led" LOC = "P118"\| IOSTANDARD = LVCMOS33 ;
	~~NET "led_anode" LOC = "P116~~"\| IOSTANDARD = LVCMOS33 ;
	</source>		</source>

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	TIMESPEC "TS_Clk" = PERIOD "Clk" 10 ns HIGH 50 %;		TIMESPEC "TS_Clk" = PERIOD "Clk" 10 ns HIGH 50 %;
	# LED		# LED
	NET "~~led_cathode~~" LOC = "C15"\| IOSTANDARD = LVCMOS33 ; #IO_L24N_1		NET "led" LOC = "C15"\| IOSTANDARD = LVCMOS33 ; #IO_L24N_1
	~~NET "led_anode" LOC = "C16"\| IOSTANDARD = LVCMOS33 ; #IO_L24P_1~~
	</source>		</source>

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	TIMESPEC "TS_Clk" = PERIOD "Clk" 10.77 ns HIGH 50 %;		TIMESPEC "TS_Clk" = PERIOD "Clk" 10.77 ns HIGH 50 %;
	# LED		# LED
	NET "~~led_cathode~~" LOC = "G15"\| IOSTANDARD = LVCMOS33 ; #IO_L41N_GCLK8_M1CASN_1		NET "led" LOC = "G15"\| IOSTANDARD = LVCMOS33 ; #IO_L41N_GCLK8_M1CASN_1
	~~NET "led_anode" LOC = "G14"\| IOSTANDARD = LVCMOS33 ; #IO_L41P_GCLK9_IRDY_M1RASN_1~~
	</source>		</source>

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	== Generate bitstream ==		== Generate bitstream ==

			=== ISE ===
	Once these two files are written, FPGA configuration file, also named "bitstream", can be generated by clicking on ''Synthetize - XST'' then ''Implement Design'' and finally ''Generate Programming File''. If all these operations are correctly done, a file with ".bit" extension will be generated.		Once these two files are written, FPGA configuration file, also named "bitstream", can be generated by clicking on ''Synthetize - XST'' then ''Implement Design'' and finally ''Generate Programming File''. If all these operations are correctly done, a file with ".bit" extension will be generated.

			=== Quartus ===

			{{Under_Construction}}

	== Configure FPGA ==		== Configure FPGA ==