PCIe FPGA loading - Revision history

KevinJ: Blanked the page

2025-10-03T13:45:55Z

Blanked the page

← Older revision		Revision as of 15:45, 3 October 2025
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	~~[[Category:FPGA]]~~
	~~[[Category: PCIe]]~~
	~~== Introduction ==~~

	~~On APF6_SP PCI express bus is used to configure the FPGA (cycloneV). This article describe how to do that.~~

	~~== Generate files ==~~

	~~=== Quartus configuration ===~~

	Your design must include the [[IMX6-CycloneV_interface_description#Qsys_.28Quartus.29_:_Avalon-MM_Cyclone_V_Hard_IP_for_PCI_Express_configuration_.28CvP.29 \| PCIe and CvP components]]. Once the project synthesized, open the menu:
	~~<pre class="config">~~
	~~File -> Convert Programming Files ...~~
	~~</pre>~~

	* In '''Output programming file''' select the '''programming file type:''' Raw Binary File (.rbf).
	* In '''Input files to convert''' clic on '''Add Files...''' and add your binary.sof file.
	* In '''Output programming file''' check the option Create CvP files (Generate binary.periph.rbf and binary.core.rbf)
	* Click on '''Generate'''

	~~You will get two files:~~

	* '''binary.periph.rbf''': peripheral config file to be loaded via serial config bus with U-Boot
	* '''binary.core.rbf''': core config file to be loaded via PCIe bus with Linux.

	~~=== Linux configuration ===~~

	~~All drivers are already selected by default in APF6's Buildroot configuration.~~

	~~== Configure the FPGA ==~~

	~~=== Peripheral configuration in uboot ===~~

	~~PCIe must be activated before Linux boot. To do that, just load the peripheral bitstream with uboot :~~

	~~<pre class="apf">~~
	~~BIOS> tftpboot ${loadaddr} 192.168.0.117:binary.periph.rbf~~
	~~BIOS> fpga load 0 ${loadaddr} ${filesize}~~
	~~</pre>~~

	~~Then boot Linux:~~
	~~<pre class="apf">~~
	~~BIOS> boot~~
	~~</pre>~~

	~~=== Core configuration in Linux ===~~

	~~The PCIe device must be seen in lspci command in Linux :~~
	~~<pre class="apf">~~
	~~# lspci~~
	~~00:00.0 PCI bridge: Device 16c3:abcd (rev 01)~~
	~~01:00.0 Unclassified device [0013]: Altera Corporation Device e001 (rev 01)~~
	~~</pre>~~

	~~You can then download the core (192.168.0.2 should be replaced with your Host PC IP address):~~
	~~<pre class="apf">~~
	~~$ tftp -g -r binary.core.rbf 192.168.0.2~~
	~~$ load_fpga output_file.core.rbf~~
	~~Altera CvP 0000:01:00.0: Now starting CvP...~~
	~~Altera CvP 0000:01:00.0: CvP successful, application layer now ready~~
	~~</pre>~~

	~~=== Automatic FPGA configuration ===~~

	~~To let apf configure the FPGA automatically at boot we have to configure U-boot and Linux as seen in the following.~~

	~~==== U-boot ====~~
	~~See the [[Target_Software_Installation#APF6_SP \| target software installation]] to know how to install a ''firmware autoload'' on U-Boot.~~

	~~==== Linux ====~~
	~~Once Linux booted, the core must be loaded via PCIe. This can be done with an init.d script:~~

	* Copy the bitstream '''firmware.core.rbf''' in target directory : '''/lib/firmware/fpga/'''
	* Create a file in '''/etc/init.d/''' named '''S80firmware''' for example.
	* Edit it with these lines:
	~~<source lang="bash">~~
	~~load_fpga /lib/firmware/fpga/firmware.core.rbf~~
	~~</source>~~
	* Then add execution right for the script :
	~~<pre class="apf">~~
	~~$ chmod +x /etc/init.d/S80firmware~~
	~~</pre>~~

	* Reboot the board:
	~~<pre class="apf">~~
	~~$ reboot~~
	~~</pre>~~

	~~== Links ==~~

FabienM: /* Automatic FPGA configuration */

2016-02-05T09:59:46Z

Automatic FPGA configuration

← Older revision		Revision as of 11:59, 5 February 2016
Line 62:		Line 62:

	=== Automatic FPGA configuration ===		=== Automatic FPGA configuration ===

			To let apf configure the FPGA automatically at boot we have to configure U-boot and Linux as seen in the following.

	==== U-boot ====		==== U-boot ====

FabienM: /* Automatic FPGA configuration */

2016-02-05T09:52:43Z

Automatic FPGA configuration

@@ Line 63: / Line 63: @@
 === Automatic FPGA configuration ===
-See the [[Target_Software_Installation#APF6_SP | target software installation]] to know how to install a ''firmware autoload'' on APF6_SP.
+==== U-boot ====
 == Links ==

FabienM: /* Configure the FPGA */

2016-02-05T09:45:58Z

Configure the FPGA

← Older revision		Revision as of 11:45, 5 February 2016
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	Altera CvP 0000:01:00.0: CvP successful, application layer now ready		Altera CvP 0000:01:00.0: CvP successful, application layer now ready
	</pre>		</pre>

			=== Automatic FPGA configuration ===

			See the [[Target_Software_Installation#APF6_SP \| target software installation]] to know how to install a ''firmware autoload'' on APF6_SP.

	== Links ==		== Links ==

FabienM: /* Core configuration in Linux */

2015-08-27T06:42:24Z

Core configuration in Linux

← Older revision		Revision as of 08:42, 27 August 2015
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	<pre class="apf">		<pre class="apf">
	$ tftp -g -r binary.core.rbf 192.168.0.2		$ tftp -g -r binary.core.rbf 192.168.0.2
	$ ~~modprobe fpgaloader~~		$ load_fpga output_file.core.rbf
	~~$ mknod /dev/altera_cvp c 249 0~~
	~~$ cat~~ output_file.core.rbf ~~> /dev/altera_cvp~~
	Altera CvP 0000:01:00.0: Now starting CvP...		Altera CvP 0000:01:00.0: Now starting CvP...
	Altera CvP 0000:01:00.0: CvP successful, application layer now ready		Altera CvP 0000:01:00.0: CvP successful, application layer now ready

FabienM: /* Introduction */

2015-06-22T11:24:08Z

Introduction

← Older revision		Revision as of 13:24, 22 June 2015
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	== Introduction ==		== Introduction ==

	On APF6_SP ~~it's possible to use the~~ PCI express bus to configure the FPGA (cycloneV). This article describe how to do that.		On APF6_SP PCI express bus is used to configure the FPGA (cycloneV). This article describe how to do that.

	== Generate files ==		== Generate files ==

FabienM: /* Quartus configuration */

2015-06-22T11:23:26Z

Quartus configuration

← Older revision		Revision as of 13:23, 22 June 2015
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	=== Quartus configuration ===		=== Quartus configuration ===

	Your design must include the PCIe and CvP components. Once the project synthesized, open the menu:		Your design must include the [[IMX6-CycloneV_interface_description#Qsys_.28Quartus.29_:_Avalon-MM_Cyclone_V_Hard_IP_for_PCI_Express_configuration_.28CvP.29 \| PCIe and CvP components]]. Once the project synthesized, open the menu:
	<pre class="config">		<pre class="config">
	File -> Convert Programming Files ...		File -> Convert Programming Files ...

WikiSysop: PCIe fpga load moved to PCIe FPGA loading

2015-03-17T10:23:32Z

PCIe fpga load moved to PCIe FPGA loading

← Older revision	Revision as of 12:23, 17 March 2015
(No difference)

WikiSysop: /* Core configuration in Linux */

2015-03-17T10:23:05Z

Core configuration in Linux

← Older revision		Revision as of 12:23, 17 March 2015
Line 53:		Line 53:
	</pre>		</pre>

	You can then download the core :		You can then download the core (192.168.0.2 should be replaced with your Host PC IP address):

	<pre class="apf">		<pre class="apf">
	$ tftp -g -r binary.core.rbf 192.168.0.~~117~~		$ tftp -g -r binary.core.rbf 192.168.0.2
	$ modprobe fpgaloader		$ modprobe fpgaloader
	$ mknod /dev/altera_cvp c 249 0		$ mknod /dev/altera_cvp c 249 0
Line 62:		Line 61:
	Altera CvP 0000:01:00.0: Now starting CvP...		Altera CvP 0000:01:00.0: Now starting CvP...
	Altera CvP 0000:01:00.0: CvP successful, application layer now ready		Altera CvP 0000:01:00.0: CvP successful, application layer now ready
	$
	</pre>		</pre>

	== Links ==		== Links ==

WikiSysop: /* Linux configuration */

2015-03-17T10:21:51Z

Linux configuration

← Older revision		Revision as of 12:21, 17 March 2015
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	=== Linux configuration ===		=== Linux configuration ===

	All drivers are already selected by default in ~~buildroot~~ configuration.		All drivers are already selected by default in APF6's Buildroot configuration.

	== Configure the FPGA ==		== Configure the FPGA ==