OPOS93 SP FPGA designing - Revision history

KevinJ: /* Requisites */

2025-10-03T16:00:45Z

Requisites

← Older revision		Revision as of 18:00, 3 October 2025
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	[[Category: FPGA]]		[[Category: FPGA]]

	== ~~Requisites~~ ==		== Prerequisites ==

	You'll need to install [[Efinity]] in order to synthetise your design for the embedded Efinix Trion T20.		You'll need to install [[Efinity]] in order to synthetise your design for the embedded Efinix Trion T20.

KevinJ at 15:54, 3 October 2025

2025-10-03T15:54:03Z

← Older revision		Revision as of 17:54, 3 October 2025
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	# Download the '''Opos93SP template project''' or the '''Opos93SP wishbone template project''' whether you need a Wishbone bus or not.		# Download the '''Opos93SP template project''' or the '''Opos93SP wishbone template project''' whether you need a Wishbone bus or not.
	# Open the project in [[Efinity]] and start hacking the generated wishbone or FlexIO Verilog modules depending on the template project you chose in the step above.		# Open the project in [[Efinity]] and start hacking the generated wishbone or FlexIO Verilog modules depending on the template project you chose in the step above.

			= JTAG Debugging =

			JTAG debugging using [[Efinity]] can be achieved following this procedure:
			# Synthetise the design (only the ''Synthetise'' step is required)
			# Generate a debug core using the "Debug Wizard" of Efinity
			# Add the signals you are interested in
			# Generate the bitstream (you can skip the ''Synthesis' step and resume from the ''Mapping'' step)
			# [[OPOS93_SP_FPGA_configuration \| Configure the FPGA]] with the generated bitstream
			# Open the Efinity debugger and attach the target

			Now you should be able to trigger acquisition, see instant signal values, etc ...

KevinJ: /* Chisel */

2025-10-03T15:26:19Z

Chisel

← Older revision		Revision as of 17:26, 3 October 2025
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	#*'''Makefile''': change your project name, change your Chisel project's directory, ...		#*'''Makefile''': change your project name, change your Chisel project's directory, ...
	#*'''generate-project.py''': IO configurations of the FPGA (see documentation from Efinix)		#*'''generate-project.py''': IO configurations of the FPGA (see documentation from Efinix)
			# Load [[Efinity]]'s environment variables (do it only one time):
			#:<pre class="host">$ source <EFINITY_PATH>/bin/setup.sh</pre>
	# Build the project		# Build the project
	#: <pre class="host"> $ make </pre>		#: <pre class="host"> $ make </pre>

KevinJ: /* Chisel */

2025-10-03T15:23:33Z

Chisel

← Older revision		Revision as of 17:23, 3 October 2025
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	# You can then hack the different files:		# You can then hack the different files:
	#*'''Makefile''': change your project name, change your Chisel project's directory, ...		#*'''Makefile''': change your project name, change your Chisel project's directory, ...
	#*'''generate-project.py''': IO configurations of the FPGA (see documentation from ~~[[Efinity]]~~)		#*'''generate-project.py''': IO configurations of the FPGA (see documentation from Efinix)
	# Build the project		# Build the project
	#: <pre class="host"> $ make </pre>		#: <pre class="host"> $ make </pre>

KevinJ: Created page with "Category: OPOS93_SP Category: FPGA == Requisites == You'll need to install Efinity in order to synthetise your design for the embedded Efinix Trion T20. == Starting from a template project == Template projects for Chisel or Verilog/VHDL development are publicly available on the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository]. == Chisel == # Install [https://www.scala-sb..."

2025-10-03T15:13:46Z

Created page with "Category: OPOS93_SP Category: FPGA == Requisites == You'll need to install Efinity in order to synthetise your design for the embedded Efinix Trion T20. == Starting from a template project == Template projects for Chisel or Verilog/VHDL development are publicly available on the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository]. == Chisel == # Install [https://www.scala-sb..."

New page

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Requisites ==

You'll need to install [[Efinity]] in order to synthetise your design for the embedded Efinix Trion T20.

== Starting from a template project ==

Template projects for [[Chisel | Chisel]] or Verilog/VHDL development are publicly available on the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository].

== Chisel ==

# Install [https://www.scala-sbt.org/download/ Scala/SBT] on your environment
# Setup a Chisel project and add the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper] as a dependency
# From the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository], copy the ''opos93sp-template'' or ''opos93sp-template-wb'' (with Wishbone bus instantiated) folder from the ''hardware'' directory.
# You can then hack the different files:
#*'''Makefile''': change your project name, change your Chisel project's directory, ...
#*'''generate-project.py''': IO configurations of the FPGA (see documentation from [[Efinity]])
# Build the project
#: <pre class="host"> $ make </pre>

== Verilog/VHDL ==

The [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository] build template projects for every releases. Those tamplate projects can be found under the asset section on [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper/-/releases the release page].

# Download the '''Opos93SP template project''' or the '''Opos93SP wishbone template project''' whether you need a Wishbone bus or not.
# Open the project in [[Efinity]] and start hacking the generated wishbone or FlexIO Verilog modules depending on the template project you chose in the step above.