OPOS6UL SP Interfaces description - Revision history

FabienM: /* Links */

2025-04-10T06:09:00Z

Links

← Older revision		Revision as of 08:09, 10 April 2025
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	* [https://www.xilinx.com/support/documentation/user_guides/ug380.pdf Spartan6 configuration] (PDF)		* [https://www.xilinx.com/support/documentation/user_guides/ug380.pdf Spartan6 configuration] (PDF)
	* [https://github.com/Martoni/pod_lib/tree/master/platforms/opos6ulsp Peripheral On Demand configuration files]		* [https://github.com/Martoni/pod_lib/tree/master/platforms/opos6ulsp Peripheral On Demand configuration files]

	[[Using_FPGA\| << FPGA general page]]		[[Using_FPGA\| << FPGA general page]]

FabienM: /* Introduction */

2021-06-02T13:17:52Z

Introduction

← Older revision		Revision as of 15:17, 2 June 2021
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	This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule. All description of this bus can be found under the i.MX6UL(L) [https://www.nxp.com/webapp/Download?colCode=IMX6ULRM reference manual] in chapter 21 (page 821).		This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule. All description of this bus can be found under the i.MX6UL(L) [https://www.nxp.com/webapp/Download?colCode=IMX6ULRM reference manual] in chapter 21 (page 821).

			FPGA used on board is an '''XC6SLX9-2CSG225'''.

	== Simplified view ==		== Simplified view ==

FabienM: /* Default configuration on CSx */

2020-07-22T08:40:48Z

Default configuration on CSx

← Older revision		Revision as of 10:40, 22 July 2020
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	* '''FPGA_DONE''': FPGA configuration is done.		* '''FPGA_DONE''': FPGA configuration is done.

			== Tutorials ==

			* [[opos6ul_sp_fpga_simple_howto \| Simple tutorial to make communication]]
	== Default configuration on CSx ==		== Default configuration on CSx ==

FabienM at 08:39, 22 July 2020

2020-07-22T08:39:15Z

← Older revision		Revision as of 10:39, 22 July 2020
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	</wavedrom>		</wavedrom>

			== code & mapping ==
	=== Pinout ===		=== Pinout ===

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	</pre>		</pre>

	== Simulation model ==
			=== Simulation model ===

	Some simulation model has been written to test eim in VHDL and in python with cocotb.		Some simulation model has been written to test eim in VHDL and in python with cocotb.

	=== VHDL ===		==== VHDL ====

	imx_read and imx_write simulation fonctions are included in POD (Peripheral On Demand) library. Available in [https://github.com/Martoni/pod_lib/blob/master/platforms/opos6ulsp/simulation/opos6ul_test_pkg.vhd platform/opos6ulsp] directory.		imx_read and imx_write simulation fonctions are included in POD (Peripheral On Demand) library. Available in [https://github.com/Martoni/pod_lib/blob/master/platforms/opos6ulsp/simulation/opos6ul_test_pkg.vhd platform/opos6ulsp] directory.

	=== Cocotb ===		==== Cocotb ====

	It's possible to simulate eim access with [https://cocotb.readthedocs.io/en/latest/introduction.html cocotb] module named [https://github.com/Martoni/cocotbext-imxeim cocotbext-imxeim].		It's possible to simulate eim access with [https://cocotb.readthedocs.io/en/latest/introduction.html cocotb] module named [https://github.com/Martoni/cocotbext-imxeim cocotbext-imxeim].

	== HDL bus wrapper ==		=== HDL bus wrapper ===

	Bus wrapper has been written in VHDL and chisel to convert EIM protocol to Wishbone bus protocol.		Bus wrapper has been written in VHDL and chisel to convert EIM protocol to Wishbone bus protocol.

	=== VHDL ===		==== VHDL ====

	A 16 bits multiplexed EIM to 16bits wishbone master bus is available in [https://github.com/Martoni/periphondemand POD] library. The VHDL sources are available following [https://github.com/Martoni/pod_lib/blob/master/library/wrappers/imx6ul_wb16_wrapper/hdl/imx6ul_wb16_wrapper.vhd this link].		A 16 bits multiplexed EIM to 16bits wishbone master bus is available in [https://github.com/Martoni/periphondemand POD] library. The VHDL sources are available following [https://github.com/Martoni/pod_lib/blob/master/library/wrappers/imx6ul_wb16_wrapper/hdl/imx6ul_wb16_wrapper.vhd this link].

	=== Chisel ===		==== Chisel ====

	A chisel package is available in module [https://github.com/Martoni/ChisArmadeus chisArmadeus] to drive Wishbone master bus with EIM bus [https://github.com/Martoni/ChisArmadeus/blob/master/src/main/scala/chisarmadeus/op6sp/op6sp.scala here].		A chisel package is available in module [https://github.com/Martoni/ChisArmadeus chisArmadeus] to drive Wishbone master bus with EIM bus [https://github.com/Martoni/ChisArmadeus/blob/master/src/main/scala/chisarmadeus/op6sp/op6sp.scala here].

	== FPGA Interrupt ==		=== FPGA Interrupt ===

	To generate an IRQ from the FPGA to the i.MX, the pin FPGA_INITB is used by default. It correspond to [[GPIOlib#Datasheet_GPIO_number_correspondance \| GPIO4_IO16]] on i.MX.		To generate an IRQ from the FPGA to the i.MX, the pin FPGA_INITB is used by default. It correspond to [[GPIOlib#Datasheet_GPIO_number_correspondance \| GPIO4_IO16]] on i.MX.

	== FPGA J2 connector mapping ==		=== FPGA J2 connector mapping ===

	Mapping of FPGA pin is given in following [[op6spJ2pinout \| csv file]].		Mapping of FPGA pin is given in following [[op6spJ2pinout \| csv file]].

FabienM: /* Introduction */

2020-01-16T15:30:37Z

Introduction

← Older revision		Revision as of 17:30, 16 January 2020
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	== Introduction ==		== Introduction ==

	This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule. All description of this bus can be found under the i.MX6UL(L) reference manual in chapter 21 (page 821).		This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule. All description of this bus can be found under the i.MX6UL(L) [https://www.nxp.com/webapp/Download?colCode=IMX6ULRM reference manual] in chapter 21 (page 821).


	== Simplified view ==		== Simplified view ==

FabienM: /* FPGA configuration protocol */

2020-01-10T10:02:19Z

FPGA configuration protocol

← Older revision		Revision as of 12:02, 10 January 2020
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	To generate an IRQ from the FPGA to the i.MX, the pin FPGA_INITB is used by default. It correspond to [[GPIOlib#Datasheet_GPIO_number_correspondance \| GPIO4_IO16]] on i.MX.		To generate an IRQ from the FPGA to the i.MX, the pin FPGA_INITB is used by default. It correspond to [[GPIOlib#Datasheet_GPIO_number_correspondance \| GPIO4_IO16]] on i.MX.

			== FPGA J2 connector mapping ==

			Mapping of FPGA pin is given in following [[op6spJ2pinout \| csv file]].

	== FPGA configuration protocol ==		== FPGA configuration protocol ==

FabienM: /* Simulation model */

2020-01-08T09:19:32Z

Simulation model

← Older revision		Revision as of 11:19, 8 January 2020
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	It's possible to simulate eim access with [https://cocotb.readthedocs.io/en/latest/introduction.html cocotb] module named [https://github.com/Martoni/cocotbext-imxeim cocotbext-imxeim].		It's possible to simulate eim access with [https://cocotb.readthedocs.io/en/latest/introduction.html cocotb] module named [https://github.com/Martoni/cocotbext-imxeim cocotbext-imxeim].

			== HDL bus wrapper ==

			Bus wrapper has been written in VHDL and chisel to convert EIM protocol to Wishbone bus protocol.

			=== VHDL ===

			A 16 bits multiplexed EIM to 16bits wishbone master bus is available in [https://github.com/Martoni/periphondemand POD] library. The VHDL sources are available following [https://github.com/Martoni/pod_lib/blob/master/library/wrappers/imx6ul_wb16_wrapper/hdl/imx6ul_wb16_wrapper.vhd this link].

			=== Chisel ===

			A chisel package is available in module [https://github.com/Martoni/ChisArmadeus chisArmadeus] to drive Wishbone master bus with EIM bus [https://github.com/Martoni/ChisArmadeus/blob/master/src/main/scala/chisarmadeus/op6sp/op6sp.scala here].

	== FPGA Interrupt ==		== FPGA Interrupt ==

FabienM: /* Default configuration on CSx */

2020-01-08T09:10:15Z

Default configuration on CSx

@@ Line 150: / Line 150: @@
 NET "irq_mngr00_gls_irq" LOC="P3" | IOSTANDARD=LVCMOS33; # FPGA_INITB
 </pre>
 == FPGA Interrupt ==

FabienM: /* FPGA configuration protocol */

2019-04-29T12:51:47Z

FPGA configuration protocol

← Older revision		Revision as of 14:51, 29 April 2019
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	== FPGA configuration protocol ==		== FPGA configuration protocol ==

			<TODO>

	== Links ==		== Links ==

FabienM: /* HDL register access examples */

2019-04-29T12:51:30Z

HDL register access examples

← Older revision		Revision as of 14:51, 29 April 2019
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	}		}
	</wavedrom>		</wavedrom>

	~~=== HDL register access examples ===~~

	=== Pinout ===		=== Pinout ===