IMX6-CycloneV interface description - Revision history

JulienB: /* Links */

2017-08-07T12:44:48Z

Links

← Older revision		Revision as of 14:44, 7 August 2017
Line 173:		Line 173:

	== Links ==		== Links ==
	~~=== In this wiki ===~~		* [[pci_debug \| '''pci_debug''': a useful commands tool to access PCIe BARx]]
	* [[pci_debug \| '''pci_debug''': a ~~usefull~~ commands tool to access PCIe BARx]]

	~~=== External ===~~

	* [http://www.altera.com/literature/ug/ug_c5_pcie_avmm.pdf Avalon-MM to PCIe interface for CycloneV]		* [http://www.altera.com/literature/ug/ug_c5_pcie_avmm.pdf Avalon-MM to PCIe interface for CycloneV]
			* [https://community.nxp.com/docs/DOC-95014 NXP PCIe i.MX6 benchmarks]

2016-03-21T14:01:10Z

Clocking without PCIe

← Older revision		Revision as of 16:01, 21 March 2016
Line 170:		Line 170:


	A blinking led example is provided in BSP under the directory '''firmware/leds/blinking_led/src/cycloneV'''.		A blinking led example is provided in BSP under the directory '''firmware/leds/blinking_led/src/cycloneV/'''.

	== Links ==		== Links ==

2016-03-21T14:00:56Z

Clocking without PCIe

← Older revision		Revision as of 16:00, 21 March 2016
Line 170:		Line 170:


	~~{{Under_Construction}}~~		A blinking led example is provided in BSP under the directory '''firmware/leds/blinking_led/src/cycloneV'''.

	== Links ==		== Links ==
	=== In this wiki ===		=== In this wiki ===

2016-03-21T12:55:43Z

← Older revision		Revision as of 14:55, 21 March 2016
Line 166:		Line 166:

	PCIe_clk input can be used to clock the entire design without using the PCIe hard ip-core. But it can't be use directly, PLL must be instancied.		PCIe_clk input can be used to clock the entire design without using the PCIe hard ip-core. But it can't be use directly, PLL must be instancied.

			[[image:apf6sp_clocking_pcie.png\|700px\|center\|thumb\|'''figure 2''' - ''Clocking with PCIe Pll description'']]


	{{Under_Construction}}		{{Under_Construction}}
	== Links ==		== Links ==

2016-02-02T16:45:31Z

FPGA pinout

@@ Line 160: / Line 160: @@
 === FPGA pinout ===
-<pre>
+FPGA pinout is the [[APF6_SP_DDR3_PINOUT#PCIe | following]]
 == Clocking without PCIe ==

2016-02-02T16:43:01Z

FPGA pinout

2016-02-02T16:42:06Z

FPGA pinout

2016-01-14T10:59:07Z

Avalon-MM Cyclone V Hard IP for PCI Express

← Older revision		Revision as of 12:59, 14 January 2016
Line 42:		Line 42:
	* Number of lanes : '''x1'''		* Number of lanes : '''x1'''
	* Reference clock frequency : '''125Mhz'''		* Reference clock frequency : '''125Mhz'''
	* Enable configuration via the PCIe link		* check "Enable configuration via the PCIe link"
			* check "Use 62.5 MHz application clock"
	* BAR0		* BAR0
	** Type: 32-bit non-prefetchable memory		** Type: 32-bit non-prefetchable memory

2016-01-14T10:47:08Z

Simplified view

← Older revision		Revision as of 12:47, 14 January 2016
Line 24:		Line 24:
	* '''nperst''': set to vcc.		* '''nperst''': set to vcc.

	* '''coreclkout''': '''~~125Mhz~~''' (by default) clock generated by quartus hard PCIe ip-core, used to clock design by defaut.		* '''coreclkout''': '''62.5Mhz''' (by default) clock generated by quartus hard PCIe ip-core, used to clock design by defaut.

	=== Qsys (Quartus 14.0) : Avalon-MM Cyclone V Hard IP for PCI Express configuration (CvP)===		=== Qsys (Quartus 14.0) : Avalon-MM Cyclone V Hard IP for PCI Express configuration (CvP)===

2015-08-26T06:41:13Z

Qsys (Quartus) : Avalon-MM Cyclone V Hard IP for PCI Express configuration (CvP)

← Older revision		Revision as of 08:41, 26 August 2015
Line 26:		Line 26:
	* '''coreclkout''': '''125Mhz''' (by default) clock generated by quartus hard PCIe ip-core, used to clock design by defaut.		* '''coreclkout''': '''125Mhz''' (by default) clock generated by quartus hard PCIe ip-core, used to clock design by defaut.

	=== Qsys (Quartus) : Avalon-MM Cyclone V Hard IP for PCI Express configuration (CvP)===		=== Qsys (Quartus 14.0) : Avalon-MM Cyclone V Hard IP for PCI Express configuration (CvP)===

	{{Note\| The example project described above can be downloaded [http://www.armadeus.com/_downloads/apf6_SP/hardware/apf6_sp_cvp_example.zip here].}}		{{Note\| The example project described above can be downloaded [http://www.armadeus.com/_downloads/apf6_SP/hardware/apf6_sp_cvp_example.zip here].}}