IMX27-Spartan3A interface description - Revision history

FabienM at 07:33, 12 February 2015

2015-02-12T07:33:59Z

← Older revision		Revision as of 09:33, 12 February 2015
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			[[Category: APF27]]
			[[Category: FPGA]]
	== Introduction ==		== Introduction ==
	This article describes the bus interface configuration to communicate between the i.MX27 processor and the Spartan3A FPGA of the APF27 board.		This article describes the bus interface configuration to communicate between the i.MX27 processor and the Spartan3A FPGA of the APF27 board.

FabienM: /* Clock */

2012-09-03T09:02:29Z

Clock

← Older revision		Revision as of 11:02, 3 September 2012
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	=== Clock ===		=== Clock ===

	The clock used to clock the fpga is CLK0 and is configured to '''~~100~~ MHz'''.		The clock used to clock the fpga is CLK0 and is configured to '''99.75 MHz'''.

	=== Chip select ===		=== Chip select ===

FabienM: /* Timings */

2012-02-03T09:00:20Z

Timings

← Older revision		Revision as of 11:00, 3 February 2012
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	=== Timings ===		=== Timings ===

	Following chronograms represent WEIM read and write configured for APF27.		Following chronograms represent WEIM read and write configured on CS5N for APF27.

	[[image:Imx27_sp3_write_timings.jpeg\|700px\|center\|thumb\|'''figure 2''' - ''WEIM Write timings'']]		[[image:Imx27_sp3_write_timings.jpeg\|700px\|center\|thumb\|'''figure 2''' - ''WEIM Write timings'']]

FabienM: /* Simplified view */

2012-01-23T10:50:25Z

Simplified view

← Older revision		Revision as of 12:50, 23 January 2012
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	Some others signals are used only for firmware download. For more informations about the FPGA wiring, see the [[Datasheet#APF27 \| APF27 schematics]] and the [http://cache.freescale.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf?fsrch=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&sr=2 i.MX27 reference manual], especially the WEIM chapter.		Some others signals are used only for firmware download. For more informations about the FPGA wiring, see the [[Datasheet#APF27 \| APF27 schematics]] and the [http://cache.freescale.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf?fsrch=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&sr=2 i.MX27 reference manual], especially the WEIM chapter.

	~~Complète~~ pinout of the interface can be found under the [[Datasheet#APF27 \| APF27 datasheet]].		Complete pinout of the interface can be found under the [[Datasheet#APF27 \| APF27 datasheet]].

	== Default configuration on CS5N ==		== Default configuration on CS5N ==

FabienM: /* Simplified view */

2012-01-23T10:50:04Z

Simplified view

← Older revision		Revision as of 12:50, 23 January 2012
Line 23:		Line 23:
	Signals in '''bold''' are used in default configuration.		Signals in '''bold''' are used in default configuration.
	Some others signals are used only for firmware download. For more informations about the FPGA wiring, see the [[Datasheet#APF27 \| APF27 schematics]] and the [http://cache.freescale.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf?fsrch=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&sr=2 i.MX27 reference manual], especially the WEIM chapter.		Some others signals are used only for firmware download. For more informations about the FPGA wiring, see the [[Datasheet#APF27 \| APF27 schematics]] and the [http://cache.freescale.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf?fsrch=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&sr=2 i.MX27 reference manual], especially the WEIM chapter.

			Complète pinout of the interface can be found under the [[Datasheet#APF27 \| APF27 datasheet]].

	== Default configuration on CS5N ==		== Default configuration on CS5N ==

FabienM: /* Pinout */

2012-01-23T10:47:39Z

Pinout

← Older revision		Revision as of 12:47, 23 January 2012
Line 83:		Line 83:

	Note : With default apf27 kernel 2.6.29.x the GPIOlib can use interrupt event, but can't configure it with ''/sys/class/gpio/gpio172/edge'' file. Interrupt must be configured under the kernel sources. The ''/sys/class/gpio/gpio172/edge'' file can be use only with [[APF9328_and_APF27_migration_to_Linux_2.6.36 \| kernel 2.6.38.x]].		Note : With default apf27 kernel 2.6.29.x the GPIOlib can use interrupt event, but can't configure it with ''/sys/class/gpio/gpio172/edge'' file. Interrupt must be configured under the kernel sources. The ''/sys/class/gpio/gpio172/edge'' file can be use only with [[APF9328_and_APF27_migration_to_Linux_2.6.36 \| kernel 2.6.38.x]].

	~~== Pinout ==~~

	~~{\| border="1" cellpadding="5" cellspacing="0" align="center"~~
	~~\|- style="background:#efefef;" align="center"~~
	~~! Schematic name !! i.MX27 gpio !! Spartan3A IO !! Spartan3A Ball !! Description~~
	~~\|- align="center"~~
	~~\| DATA[0] \|\| - \|\| IO_L06P_2/D7 \|\| T5 \|\| Data bus 0~~
	~~\|- align="center"~~
	~~\| DATA[1] \|\| - \|\| IO_L06N_2/D6 \|\| T6 \|\| Data bus 1~~
	~~\|- align="center"~~
	~~\| DATA[2] \|\| - \|\| IO_L08P_2/D5 \|\| P7 \|\| Data bus 2~~
	~~\|- align="center"~~
	~~\| DATA[3] \|\| - \|\| IO_L08N_2/D4 \|\| N8 \|\| Data bus 3~~
	~~\|- align="center"~~
	~~\| DATA[4] \|\| - \|\| IO_L17N_2/D3 \|\| P12 \|\| Data bus 4~~
	~~\|- align="center"~~
	~~\| DATA[5] \|\| - \|\| IO_L18P_2/D2 \|\| T13 \|\| Data bus 5~~
	~~\|- align="center"~~
	~~\| DATA[6] \|\| - \|\| IO_L18N_2/D1 \|\| R13 \|\| Data bus 6~~
	~~\|- align="center"~~
	~~\| DATA[7] \|\| - \|\| IO_L20P_2/D0/DIN/MISO \|\| T14 \|\| Data bus 7~~
	~~\|- align="center"~~
	~~\| DATA[8] \|\| - \|\| IO_L04N_2/VS0 \|\| P5 \|\| Data bus 8~~
	~~\|- align="center"~~
	~~\| DATA[9] \|\| - \|\| IO_L04P_2/VS1 \|\| N6 \|\| Data bus 9~~
	~~\|- align="center"~~
	~~\| DATA[10] \|\| - \|\| IO_L03N_2/VS2 \|\| T3 \|\| Data bus 10~~
	~~\|- align="center"~~
	~~\| DATA[11] \|\| - \|\| IO_L15P_2/AWAKE \|\| T11 \|\| Data bus 11~~
	~~\|- align="center"~~
	~~\| DATA[12] \|\| - \|\| IO_L05P_2 \|\| T4 \|\| Data bus 12~~
	~~\|- align="center"~~
	~~\| DATA[13] \|\| - \|\| IO_L05N_2 \|\| R5 \|\| Data bus 13~~
	~~\|- align="center"~~
	~~\| DATA[14] \|\| - \|\| IO_L13N_2 \|\| M10 \|\| Data bus 14~~
	~~\|- align="center"~~
	~~\| DATA[15] \|\| - \|\| IO_L14P_2 \|\| T10 \|\| Data bus 15~~
	~~\|- align="center"~~

	~~\| ADDR1 \|\| - \|\| IP_21/VREF_2 \|\|N5 \|\| Address bus pin 1~~
	~~\|- align="center"~~
	~~\| ADDR2 \|\| - \|\| IP_22 \|\|L7 \|\| Address bus pin 2~~
	~~\|- align="center"~~
	~~\| ADDR3 \|\| - \|\| IP_23/VREF_2 \|\|M7 \|\| Address bus pin 3~~
	~~\|- align="center"~~
	~~\| ADDR4 \|\| - \|\| IP_24/VREF_2 \|\|M8 \|\| Address bus pin 4~~
	~~\|- align="center"~~
	~~\| ADDR5 \|\| - \|\| IP_25 \|\|L8 \|\| Address bus pin 5~~
	~~\|- align="center"~~
	~~\| ADDR6 \|\| - \|\| IP_26/VREF_2 \|\|L9 \|\| Address bus pin 6~~
	~~\|- align="center"~~
	~~\| ADDR7 \|\| - \|\| IP_27/VREF_2 \|\|L10 \|\| Address bus pin 7~~
	~~\|- align="center"~~
	~~\| ADDR8 \|\| - \|\| IP_28/VREF_2 \|\|M11 \|\| Address bus pin 8~~
	~~\|- align="center"~~
	~~\| ADDR9 \|\| - \|\| IO_L16P_2 \|\|P11 \|\| Address bus pin 9~~
	~~\|- align="center"~~
	~~\| ADDR10 \|\| - \|\| IO_L16N_2 \|\|N11 \|\| Address bus pin 10~~
	~~\|- align="center"~~
	~~\| ADDR11 \|\| - \|\| IO_L19P_2 \|\|N12 \|\| Address bus pin 11~~
	~~\|- align="center"~~
	~~\| ADDR12 \|\| - \|\| IO_L19N_2 \|\|P13 \|\| Address bus pin 12~~
	~~\|- align="center"~~
	~~\| CS4N_DTACK \|\| PF21 \|\| IO_L03P_2/RDWR_B \|\|R3 \|\| Chip select 4~~
	~~\|- align="center"~~
	~~\| CS5N \|\| PF22 \|\|IO_L14N_2/MOSI/CSI_B \|\|P10 \|\| Chip select 5~~
	~~\|- align="center"~~
	~~\| CS1N \|\| - \|\| IO_L10N_2/GCLK15 \|\| T8 \|\| Chip select 1~~
	~~\|- align="center"~~
	~~\| EB0N \|\| - \|\| IO_L11N_2/GCLK1 \|\| P9 \|\| Enable Byte 0~~
	~~\|- align="center"~~
	~~\| EB1N \|\| - \|\| IO_L10P_2/GCLK14 \|\| P8 \|\| Enable Byte 1~~
	~~\|- align="center"~~
	~~\| OEN \|\| - \|\| IO_L12P_2/GCLK2 \|\| R9 \|\| Output Enable bit~~
	~~\|- align="center"~~
	~~\| DMA_GRANT# \|\| PD27 \|\| IO_L09P_2/GCLK12 \|\| R7 \|\| DMA access~~
	~~\|- align="center"~~
	~~\| DMA_REQ# \|\| PD25 \|\| IO_L12N_2/GCLK3 \|\| T9 \|\| DMA access~~
	~~\|- align="center"~~
	~~\| CLKO \|\| PF15 \|\| IO_L11P_2/GCLK0\|\|N9 \|\| Clock~~
	~~\|- align="center"~~
	~~\| FPGA_INIT \|\| PF12 \|\| IO_L17P_2/INIT_B \|\| T12 \|\| Used by default for interrupts~~

	\|}

FabienM at 09:54, 23 January 2012

2012-01-23T09:54:07Z

@@ Line 75: / Line 75: @@
 By default, the wishbone bus is proposed on the spartan3A fpga. A WEIM to Wishbone wrapper is used, which is available under POD default libraries in wrappers lib. The component is named imx27_wb16_wrapper.
 == The FPGA interrupt ==
@@ Line 81: / Line 83: @@
 Note : With default apf27 kernel 2.6.29.x the GPIOlib can use interrupt event, but can't configure it with ''/sys/class/gpio/gpio172/edge'' file. Interrupt must be configured under the kernel sources. The ''/sys/class/gpio/gpio172/edge'' file can be use only with [[APF9328_and_APF27_migration_to_Linux_2.6.36 | kernel 2.6.38.x]].

Salocin68 at 13:46, 20 January 2012

2012-01-20T13:46:19Z

← Older revision		Revision as of 15:46, 20 January 2012
Line 1:		Line 1:

	== Introduction ==		== Introduction ==
	This article ~~describe~~ the bus interface configuration to communicate between i.MX27 processor and Spartan3A FPGA.		This article describes the bus interface configuration to communicate between the i.MX27 processor and the Spartan3A FPGA of the APF27 board.

	== Simplified view ==		== Simplified view ==
Line 10:		Line 9:

	* '''DATA[15:0]''': Data bus.		* '''DATA[15:0]''': Data bus.
	* '''ADDR[12:1]''': Address bus. All access are ~~down~~ in 16bits, ~~then pin 0~~ is not used and not ~~plugged~~.		* '''ADDR[12:1]''': Address bus. All access are done in 16bits, this means that A0 is not used and not connected.
	* CS4N_DTACK: Chip select 4 (0xD400_0000 to 0xD5FF_FFFF ) or Data Transmit ACKnowledge. This signal can be used as DTACK for asynchronous access with chip select 5.		* CS4N_DTACK: Chip select 4 (0xD400_0000 to 0xD5FF_FFFF ) or Data Transmit ACKnowledge. This signal can be used as DTACK for asynchronous access with chip select 5.
	* '''CS5N''': Chip select 5 (0xD600_0000 to 0xD7FF_FFFF ). Configured by default for FPGA communication.		* '''CS5N''': Chip select 5 (0xD600_0000 to 0xD7FF_FFFF ). Chip select 5. Configured by default for FPGA communication.
	* CS1N: Chip select 1 (0xC800_0000 to 0xCFFF_FFFF ).		* CS1N: Chip select 1 (0xC800_0000 to 0xCFFF_FFFF ). Chip select 1
	* '''EB0N''', EB1N: For Enable Byte, write signal for lower byte and upper byte on data bus.		* '''EB0N''', EB1N: For Enable Byte, write signal for lower byte and upper byte on data bus.
	* '''OEN''': For Output Enable bit, read signal.		* '''OEN''': For Output Enable bit, read signal.
	* DMA_GRANT#: ~~Signals to use~~ DMA ~~on i.MX~~.		* DMA_GRANT#: Required for DMA access (future development).
	* DMA_REQ#: ~~Signals to use~~ DMA ~~on i.MX.~~		* DMA_REQ#: Required for DMA access (future development)
	Not part of WEIM bus :		Not part of WEIM bus :
	* '''CLKO''': Clock generated by i.MX. Used as general clock by the FPGA.		* '''CLKO''': Clock generated by the i.MX. Used as a general clock by the FPGA.
	* FPGA_INIT: Not part of i.MX27 WEIM bus but used by default for interrupts (GPIO PF12).		* FPGA_INIT: Not part of i.MX27 WEIM bus but used by default for interrupts (GPIO PF12).

	Signals in '''bold''' are ~~signals~~ used in default configuration.		Signals in '''bold''' are used in default configuration.
	Some others signals are used only for ~~fpga configuration~~. For more informations about the FPGA wiring, see the [[Datasheet#APF27 \| APF27 schematics]] and the [http://cache.freescale.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf?fsrch=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&sr=2 i.MX27 reference manual], especially the WEIM chapter.		Some others signals are used only for firmware download. For more informations about the FPGA wiring, see the [[Datasheet#APF27 \| APF27 schematics]] and the [http://cache.freescale.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf?fsrch=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&sr=2 i.MX27 reference manual], especially the WEIM chapter.

	== Default configuration on CS5N ==		== Default configuration on CS5N ==
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	\| '''0xD600 0000''' \|\| '''0xD7FF FFFF''' \|\| '''32M''' \|\| '''WEIM External Memory (CS5)'''		\| '''0xD600 0000''' \|\| '''0xD7FF FFFF''' \|\| '''32M''' \|\| '''WEIM External Memory (CS5)'''
	\|}		\|}
	~~It's possible to use the other~~ chip select (CS1 and CS4) to extend memory domain or to use different timing configuration with the same Address/Data bus signals.		Other chip select (CS1 and CS4) can be used to extend the memory domain or to use different timing configuration with the same Address/Data bus signals.
	The default bus configuration for the APF27 can be found in the file apf27.h in u-boot sources : buildroot/target/device/armadeus/apf27/apf27-u-boot-1.3.4.h		The default bus configuration for the APF27 can be found in the file apf27.h in u-boot sources : buildroot/target/device/armadeus/apf27/apf27-u-boot-1.3.4.h

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	=== Timings ===		=== Timings ===

	Following chronograms ~~represents~~ WEIM read and write configured for APF27.		Following chronograms represent WEIM read and write configured for APF27.

	[[image:Imx27_sp3_write_timings.jpeg\|700px\|center\|thumb\|'''figure 2''' - ''WEIM Write timings'']]		[[image:Imx27_sp3_write_timings.jpeg\|700px\|center\|thumb\|'''figure 2''' - ''WEIM Write timings'']]
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	=== FPGA side ===		=== FPGA side ===

	By default, the wishbone bus is ~~used under~~ the spartan3A fpga. ~~Then a~~ WEIM to Wishbone wrapper is used, ~~this wrapper~~ is available under POD default libraries in wrappers lib. The component is named imx27_wb16_wrapper.		By default, the wishbone bus is proposed on the spartan3A fpga. A WEIM to Wishbone wrapper is used, which is available under POD default libraries in wrappers lib. The component is named imx27_wb16_wrapper.

	== The FPGA interrupt ==		== The FPGA interrupt ==

	By default under [http://periphondemand.sourceforge.net/ POD] the pin '''FPGA_INIT''' (PF12) is used for the ~~interrupts~~ manager ''irq_mngr''. For simple user application the gpio can be used with the [[GPIOlib]] interface, the gpio number will then be (6-1)x32+12 = '''172'''.		By default under [http://periphondemand.sourceforge.net/ POD] the pin '''FPGA_INIT''' (PF12) is used for the interrupt manager ''irq_mngr''. For simple user application the gpio can be used with the [[GPIOlib]] interface, the gpio number will then be (6-1)x32+12 = '''172'''.

	Note : With default apf27 kernel 2.6.29.x the GPIOlib can use interrupt event, but can't configure it with ''/sys/class/gpio/gpio172/edge'' file. Interrupt must be configured under the kernel sources. The ''/sys/class/gpio/gpio172/edge'' file can be use only with [[APF9328_and_APF27_migration_to_Linux_2.6.36 \| kernel 2.6.38.x]].		Note : With default apf27 kernel 2.6.29.x the GPIOlib can use interrupt event, but can't configure it with ''/sys/class/gpio/gpio172/edge'' file. Interrupt must be configured under the kernel sources. The ''/sys/class/gpio/gpio172/edge'' file can be use only with [[APF9328_and_APF27_migration_to_Linux_2.6.36 \| kernel 2.6.38.x]].

FabienM at 11:01, 20 January 2012

2012-01-20T11:01:14Z

← Older revision		Revision as of 13:01, 20 January 2012
Line 1:		Line 1:
	~~{{Under_Construction}}~~
	== Introduction ==		== Introduction ==
	This article describe the bus interface configuration to communicate between i.MX27 processor and Spartan3A FPGA.		This article describe the bus interface configuration to communicate between i.MX27 processor and Spartan3A FPGA.

FabienM at 10:53, 20 January 2012

2012-01-20T10:53:04Z

@@ Line 1: / Line 1: @@
   {{Under_Construction}}
 This article describe the bus interface configuration to communicate between i.MX27 processor and Spartan3A FPGA.
 [[image:Imx27-spartan3A.jpg|700px|center|thumb|'''figure 1''' - ''i.MX27-Spartan3A bus description'']]
@@ Line 6: / Line 9: @@
 Figure 1 is a simplified view of [[Datasheet#APF27 | apf27 schematics]] (page 11). Signals are :
-* CLKO: Clock generated by i.MX. Used as general clock by the FPGA.
+* '''DATA[15:0]''': Data bus.
-* DATA[15:0]: Data bus.
+* '''ADDR[12:1]''': Address bus. All access are down in 16bits, then pin 0 is not used and not plugged.
 * CS4N_DTACK: Chip select 4 (0xD400_0000 to 0xD5FF_FFFF ) or Data Transmit ACKnowledge. This signal can be used as DTACK for asynchronous access with chip select 5.
 * '''CS5N''': Chip select 5 (0xD600_0000 to 0xD7FF_FFFF ). Configured by default for FPGA communication.
 * CS1N: Chip select 1 (0xC800_0000 to 0xCFFF_FFFF ).
-* EB0N, EB1N: For Enable Byte, write signal for lower byte and upper byte on data bus.
+* '''EB0N''', EB1N: For Enable Byte, write signal for lower byte and upper byte on data bus.
-* OEN: For Output Enable bit, read signal.
+* '''OEN''': For Output Enable bit, read signal.
 * DMA_GRANT#: Signals to use DMA on i.MX.
 * DMA_REQ#: Signals to use DMA on i.MX.
-* ''FPGA_INIT'': Not part of i.MX27 WEIM bus but used by default for interrupts (GPIO PF12).
+Not part of WEIM bus :
-Some others signals are used only for fpga configuration. For more informations about the FPGA wiring, see the [[Datasheet#APF27 | APF27 schematics]] and the [http://cache.freescale.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf?fsrch=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation&sr=2 i.MX27 reference manual], especially the WEIM chapter.
+=== Timings ===

← Older revision		Revision as of 12:47, 23 January 2012
Line 83:		Line 83:

	Note : With default apf27 kernel 2.6.29.x the GPIOlib can use interrupt event, but can't configure it with ''/sys/class/gpio/gpio172/edge'' file. Interrupt must be configured under the kernel sources. The ''/sys/class/gpio/gpio172/edge'' file can be use only with [[APF9328_and_APF27_migration_to_Linux_2.6.36 \| kernel 2.6.38.x]].		Note : With default apf27 kernel 2.6.29.x the GPIOlib can use interrupt event, but can't configure it with ''/sys/class/gpio/gpio172/edge'' file. Interrupt must be configured under the kernel sources. The ''/sys/class/gpio/gpio172/edge'' file can be use only with [[APF9328_and_APF27_migration_to_Linux_2.6.36 \| kernel 2.6.38.x]].

	~~== Pinout ==~~

	~~{\| border="1" cellpadding="5" cellspacing="0" align="center"~~
	~~\|- style="background:#efefef;" align="center"~~
	~~! Schematic name !! i.MX27 gpio !! Spartan3A IO !! Spartan3A Ball !! Description~~
	~~\|- align="center"~~
	~~\| DATA[0] \|\| - \|\| IO_L06P_2/D7 \|\| T5 \|\| Data bus 0~~
	~~\|- align="center"~~
	~~\| DATA[1] \|\| - \|\| IO_L06N_2/D6 \|\| T6 \|\| Data bus 1~~
	~~\|- align="center"~~
	~~\| DATA[2] \|\| - \|\| IO_L08P_2/D5 \|\| P7 \|\| Data bus 2~~
	~~\|- align="center"~~
	~~\| DATA[3] \|\| - \|\| IO_L08N_2/D4 \|\| N8 \|\| Data bus 3~~
	~~\|- align="center"~~
	~~\| DATA[4] \|\| - \|\| IO_L17N_2/D3 \|\| P12 \|\| Data bus 4~~
	~~\|- align="center"~~
	~~\| DATA[5] \|\| - \|\| IO_L18P_2/D2 \|\| T13 \|\| Data bus 5~~
	~~\|- align="center"~~
	~~\| DATA[6] \|\| - \|\| IO_L18N_2/D1 \|\| R13 \|\| Data bus 6~~
	~~\|- align="center"~~
	~~\| DATA[7] \|\| - \|\| IO_L20P_2/D0/DIN/MISO \|\| T14 \|\| Data bus 7~~
	~~\|- align="center"~~
	~~\| DATA[8] \|\| - \|\| IO_L04N_2/VS0 \|\| P5 \|\| Data bus 8~~
	~~\|- align="center"~~
	~~\| DATA[9] \|\| - \|\| IO_L04P_2/VS1 \|\| N6 \|\| Data bus 9~~
	~~\|- align="center"~~
	~~\| DATA[10] \|\| - \|\| IO_L03N_2/VS2 \|\| T3 \|\| Data bus 10~~
	~~\|- align="center"~~
	~~\| DATA[11] \|\| - \|\| IO_L15P_2/AWAKE \|\| T11 \|\| Data bus 11~~
	~~\|- align="center"~~
	~~\| DATA[12] \|\| - \|\| IO_L05P_2 \|\| T4 \|\| Data bus 12~~
	~~\|- align="center"~~
	~~\| DATA[13] \|\| - \|\| IO_L05N_2 \|\| R5 \|\| Data bus 13~~
	~~\|- align="center"~~
	~~\| DATA[14] \|\| - \|\| IO_L13N_2 \|\| M10 \|\| Data bus 14~~
	~~\|- align="center"~~
	~~\| DATA[15] \|\| - \|\| IO_L14P_2 \|\| T10 \|\| Data bus 15~~
	~~\|- align="center"~~

	~~\| ADDR1 \|\| - \|\| IP_21/VREF_2 \|\|N5 \|\| Address bus pin 1~~
	~~\|- align="center"~~
	~~\| ADDR2 \|\| - \|\| IP_22 \|\|L7 \|\| Address bus pin 2~~
	~~\|- align="center"~~
	~~\| ADDR3 \|\| - \|\| IP_23/VREF_2 \|\|M7 \|\| Address bus pin 3~~
	~~\|- align="center"~~
	~~\| ADDR4 \|\| - \|\| IP_24/VREF_2 \|\|M8 \|\| Address bus pin 4~~
	~~\|- align="center"~~
	~~\| ADDR5 \|\| - \|\| IP_25 \|\|L8 \|\| Address bus pin 5~~
	~~\|- align="center"~~
	~~\| ADDR6 \|\| - \|\| IP_26/VREF_2 \|\|L9 \|\| Address bus pin 6~~
	~~\|- align="center"~~
	~~\| ADDR7 \|\| - \|\| IP_27/VREF_2 \|\|L10 \|\| Address bus pin 7~~
	~~\|- align="center"~~
	~~\| ADDR8 \|\| - \|\| IP_28/VREF_2 \|\|M11 \|\| Address bus pin 8~~
	~~\|- align="center"~~
	~~\| ADDR9 \|\| - \|\| IO_L16P_2 \|\|P11 \|\| Address bus pin 9~~
	~~\|- align="center"~~
	~~\| ADDR10 \|\| - \|\| IO_L16N_2 \|\|N11 \|\| Address bus pin 10~~
	~~\|- align="center"~~
	~~\| ADDR11 \|\| - \|\| IO_L19P_2 \|\|N12 \|\| Address bus pin 11~~
	~~\|- align="center"~~
	~~\| ADDR12 \|\| - \|\| IO_L19N_2 \|\|P13 \|\| Address bus pin 12~~
	~~\|- align="center"~~
	~~\| CS4N_DTACK \|\| PF21 \|\| IO_L03P_2/RDWR_B \|\|R3 \|\| Chip select 4~~
	~~\|- align="center"~~
	~~\| CS5N \|\| PF22 \|\|IO_L14N_2/MOSI/CSI_B \|\|P10 \|\| Chip select 5~~
	~~\|- align="center"~~
	~~\| CS1N \|\| - \|\| IO_L10N_2/GCLK15 \|\| T8 \|\| Chip select 1~~
	~~\|- align="center"~~
	~~\| EB0N \|\| - \|\| IO_L11N_2/GCLK1 \|\| P9 \|\| Enable Byte 0~~
	~~\|- align="center"~~
	~~\| EB1N \|\| - \|\| IO_L10P_2/GCLK14 \|\| P8 \|\| Enable Byte 1~~
	~~\|- align="center"~~
	~~\| OEN \|\| - \|\| IO_L12P_2/GCLK2 \|\| R9 \|\| Output Enable bit~~
	~~\|- align="center"~~
	~~\| DMA_GRANT# \|\| PD27 \|\| IO_L09P_2/GCLK12 \|\| R7 \|\| DMA access~~
	~~\|- align="center"~~
	~~\| DMA_REQ# \|\| PD25 \|\| IO_L12N_2/GCLK3 \|\| T9 \|\| DMA access~~
	~~\|- align="center"~~
	~~\| CLKO \|\| PF15 \|\| IO_L11P_2/GCLK0\|\|N9 \|\| Clock~~
	~~\|- align="center"~~
	~~\| FPGA_INIT \|\| PF12 \|\| IO_L17P_2/INIT_B \|\| T12 \|\| Used by default for interrupts~~

	\|}