Ho! No FPGA-reset button on armadeus card. - Revision history

FabienM at 07:35, 12 February 2015

2015-02-12T07:35:14Z

← Older revision		Revision as of 09:35, 12 February 2015
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	{{Under Construction}}		{{Under Construction}}
			[[Category: FPGA]]
	That is a constant comment about the armadeus [[APF9328]] board. Most of the FPGA designers learn that it's mandatory to use a reset in each module with structure like it:		That is a constant comment about the armadeus [[APF9328]] board. Most of the FPGA designers learn that it's mandatory to use a reset in each module with structure like it:

FabienM: /* Generate the reset internally */

2011-04-27T08:13:23Z

Generate the reset internally

← Older revision		Revision as of 10:13, 27 April 2011
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	== Generate the reset internally ==		== Generate the reset internally ==

			=== VHDL tricks ===

	But it is also possible to use initial state of the FPGA after configuration with this code:		But it is also possible to use initial state of the FPGA after configuration with this code:
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	end architecture clock_and_reset_gen_1;		end architecture clock_and_reset_gen_1;
			</source>

			=== Xilinx template ===

			Xilinx provide a reset generator under its FPGA, it can be instanciated with this vhdl template :

			<source lang="VHDL" >
			TODO
	</source>		</source>

	[[Category:FPGA]]		[[Category:FPGA]]

JulienB at 15:46, 1 November 2009

2009-11-01T15:46:53Z

← Older revision		Revision as of 17:46, 1 November 2009
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	end architecture clock_and_reset_gen_1;		end architecture clock_and_reset_gen_1;
	</source>		</source>

			[[Category:FPGA]]

JulienB at 15:46, 1 November 2009

2009-11-01T15:46:03Z

← Older revision		Revision as of 17:46, 1 November 2009
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	{{Under Construction}}		{{Under Construction}}

	That is a constant comment about the armadeus ~~apf9328 card~~. Most of FPGA ~~designer~~ learn that it's mandatory to use a reset in each module with structure like it:		That is a constant comment about the armadeus [[APF9328]] board. Most of the FPGA designers learn that it's mandatory to use a reset in each module with structure like it:

	<source lang="vhdl">		<source lang="vhdl">
Line 14:		Line 14:
	</source>		</source>

	But by default there is no reset button on ~~card~~, then what to do ?		But by default there is no reset button on the board, then what to do ?

	== Plug a reset button ==		== Plug a reset button ==

	Of course it's possible to solder a reset button on card, there are a large amount of I/O on connector and one can ~~serve to do it~~.		Of course it's possible to solder a reset button on card, there are a large amount of I/O on connector and one can be used for this usage.

	== Generate the reset ~~internal~~ ==		== Generate the reset internally ==

	But it is possible to use initial state of ~~fpga~~ after configuration with this code:		But it is also possible to use initial state of the FPGA after configuration with this code:

	{{Warning\| This code work ~~only~~ with FPGA, because states of flip-flop after configuration is defined to '0'. This can't work with CPLD for example because beginning state is unknown.}}		{{Warning\| This code only work with FPGA, because states of flip-flop after configuration is defined to '0'. This can't work with CPLD for example because beginning state is unknown.}}

	<source lang="VHDL">		<source lang="VHDL">

SonZerro: Ho! A second template exists!

2009-08-05T09:32:10Z

Ho! A second template exists!

← Older revision		Revision as of 11:32, 5 August 2009
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	{{~~Under_Construction~~}}		{{Under Construction}}

	That is a constant comment about the armadeus apf9328 card. Most of FPGA designer learn that it's mandatory to use a reset in each module with structure like it:		That is a constant comment about the armadeus apf9328 card. Most of FPGA designer learn that it's mandatory to use a reset in each module with structure like it:

FabienM: /* Generate the reset internal */

2009-03-25T09:26:06Z

Generate the reset internal

← Older revision		Revision as of 11:26, 25 March 2009
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	But it is possible to use initial state of fpga after configuration with this code:		But it is possible to use initial state of fpga after configuration with this code:

			{{Warning\| This code work only with FPGA, because states of flip-flop after configuration is defined to '0'. This can't work with CPLD for example because beginning state is unknown.}}

	<source lang="VHDL">		<source lang="VHDL">

FabienM at 10:58, 23 March 2009

2009-03-23T10:58:08Z

← Older revision		Revision as of 12:58, 23 March 2009
Line 1:		Line 1:
	{{Under_Construction}}		{{Under_Construction}}

	That is a constant comment about the armadeus apf9328 card. Most of FPGA designer learn that it's mandatory to use a reset in each module with structure like it:		That is a constant comment about the armadeus apf9328 card. Most of FPGA designer learn that it's mandatory to use a reset in each module with structure like it:

FabienM at 10:57, 23 March 2009

2009-03-23T10:57:44Z

← Older revision		Revision as of 12:57, 23 March 2009
Line 1:		Line 1:
			{{Under_Construction}}
	That is a constant comment about the armadeus apf9328 card. Most of FPGA designer learn that it's mandatory to use a reset in each module with structure like it:		That is a constant comment about the armadeus apf9328 card. Most of FPGA designer learn that it's mandatory to use a reset in each module with structure like it:

FabienM at 16:20, 20 March 2009

2009-03-20T16:20:48Z

← Older revision		Revision as of 18:20, 20 March 2009
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	~~{{Under_Construction}}~~		That is a constant comment about the armadeus apf9328 card. Most of FPGA designer learn that it's mandatory to use a reset in each module with structure like it:

	~~Ask FabM~~ to ~~finish~~ it!		<source lang="vhdl">
			myprocess : process (clk,reset)
			begin
			if reset = '1' then
			-- init values
			elsif rising_edge(clk) then
			-- processing code
			end if;
			end process myprocess;
			</source>

			But by default there is no reset button on card, then what to do ?

			== Plug a reset button ==

			Of course it's possible to solder a reset button on card, there are a large amount of I/O on connector and one can serve to do it.

			== Generate the reset internal ==

			But it is possible to use initial state of fpga after configuration with this code:

			<source lang="VHDL">
			---------------------------------------------------------------------------
			Entity clock_and_reset_gen is
			---------------------------------------------------------------------------
			generic(
			invert_reset : std_logic := '0' -- 0 : not invert, 1 invert
			);
			port
			(
			-- external signals
			ext_clk : in std_logic ;
			--internal generated signals
			gls_clk : out std_logic ;
			gls_reset : out std_logic
			);
			end entity;

			---------------------------------------------------------------------------
			Architecture clock_and_reset_gen_1 of clock_and_reset_gen is
			---------------------------------------------------------------------------

			signal dly: std_logic := '0';
			signal rst: std_logic := '0';
			signal int_reset : std_logic;

			begin

			int_reset <= '0';
			----------------------------------------------------------------------------
			-- RESET signal generator.
			----------------------------------------------------------------------------
			process(ext_clk)
			begin
			if(rising_edge(ext_clk)) then
			dly <= ( not(int_reset) and dly and not(rst) )
			or ( not(int_reset) and not(dly) and rst );

			rst <= ( not(int_reset) and not(dly) and not(rst) );
			end if;
			end process;

			gls_clk <= ext_clk;
			gls_reset <= rst xor invert_reset ;

			end architecture clock_and_reset_gen_1;
			</source>

FabienM: New page: {{Under_Construction}} Ask FabM to finish it!

2009-03-19T22:14:10Z

New page: {{Under_Construction}} Ask FabM to finish it!

New page

{{Under_Construction}}

Ask FabM to finish it!