Chisel - Revision history

FabienM: /* Armadeus Library */

2019-11-12T11:03:31Z

Armadeus Library

← Older revision		Revision as of 13:03, 12 November 2019
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	All chisel modules presented here are wrote in Chisel3 and must be "published localy" to be used.		All chisel modules presented here are wrote in Chisel3 and must be "published localy" to be used.

			== ChisArmadeus ==

			* [https://github.com/Martoni/ChisArmadeus ChisArmadeus]

			This package contain specific armadeus code to drive FPGA soldered on apf boards.


	== WbPlumbing ==		== WbPlumbing ==

FabienM: /* WbPlumbing */

2019-10-03T12:20:03Z

WbPlumbing

← Older revision		Revision as of 14:20, 3 October 2019
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	This module is used to do the Wishbone plumbing across different wishbones master and slave modules. It can generate Intercon as described in the [https://www.librecores.org/fossi-foundation/wishbone wishbone documentation].		This module is used to do the Wishbone plumbing across different wishbones master and slave modules. It can generate Intercon as described in the [https://www.librecores.org/fossi-foundation/wishbone wishbone documentation].


	== spi2wb ==		== spi2wb ==

FabienM: /* Armadeus Library */

2019-10-03T12:18:08Z

Armadeus Library

← Older revision		Revision as of 14:18, 3 October 2019
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	= Armadeus Library =		= Armadeus Library =

	All chisel ~~module~~ presented here are wrote in Chisel3 and must be "published localy" to be used.		All chisel modules presented here are wrote in Chisel3 and must be "published localy" to be used.

	== WbPlumbing ==		== WbPlumbing ==

FabienM at 12:17, 3 October 2019

2019-10-03T12:17:46Z

← Older revision		Revision as of 14:17, 3 October 2019
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	Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the [https://www.scala-lang.org/ Scala] programming language, providing designers with the power of a modern programming language to write complex, parametrizable circuit generators that produce synthesizable [https://en.wikipedia.org/wiki/Verilog Verilog]. This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the Chisel Standard Library, raising the level of abstraction in design while retaining fine-grained control.		Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the [https://www.scala-lang.org/ Scala] programming language, providing designers with the power of a modern programming language to write complex, parametrizable circuit generators that produce synthesizable [https://en.wikipedia.org/wiki/Verilog Verilog]. This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the Chisel Standard Library, raising the level of abstraction in design while retaining fine-grained control.

			Chisel is used in some internal Armadeus project. This page list some opensourced chisel components written by Armadeus.

			= Armadeus Library =

			All chisel module presented here are wrote in Chisel3 and must be "published localy" to be used.

			== WbPlumbing ==

			* [https://www.librecores.org/Martoni/wbplumbing WbPlumbing]

			This module is used to do the Wishbone plumbing across different wishbones master and slave modules. It can generate Intercon as described in the [https://www.librecores.org/fossi-foundation/wishbone wishbone documentation].


			== spi2wb ==

			* [https://www.librecores.org/Martoni/spi2wb spi2wb]

			spi2wb is a Wisbone master driven by SPI. It permit read/write under a design with a simple spi master.

			== MDIO ==

			* [https://www.librecores.org/Martoni/wbmdio MDIO]

			MDIO is a Wishbone slave used to write frames on phy mdio bus.

FabienM: Created page with "= Introduction = Introduction from the [https://www.chisel-lang.org/ official website]. Chisel is a hardware design language that facilitates advanced circuit generation and..."

2019-10-03T11:46:21Z

Created page with "= Introduction = Introduction from the [https://www.chisel-lang.org/ official website]. Chisel is a hardware design language that facilitates advanced circuit generation and..."

New page

= Introduction =

Introduction from the [https://www.chisel-lang.org/ official website].

Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the [https://www.scala-lang.org/ Scala] programming language, providing designers with the power of a modern programming language to write complex, parametrizable circuit generators that produce synthesizable [https://en.wikipedia.org/wiki/Verilog Verilog]. This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the Chisel Standard Library, raising the level of abstraction in design while retaining fine-grained control.