APF6 SP The full howto - Revision history

FabienM: /* Generate bitstream with Quartus */

2019-11-12T13:56:52Z

Generate bitstream with Quartus

← Older revision		Revision as of 15:56, 12 November 2019
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	+ Analysis & Synthesis		+ Analysis & Synthesis
	</pre>		</pre>
			{{Note\| If you have a synthesis error here with 19.1 be sure that you are using your [[Quartus_installation_on_Linux#Perl_Getopt::Long \| perl distribution]].}}
	== Pinout ==		== Pinout ==

FabienM: /* Adding the button and LED (PIO) */

2019-11-12T13:11:49Z

Adding the button and LED (PIO)

← Older revision		Revision as of 15:11, 12 November 2019
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	Peripherals		Peripherals
	PIO (Parallel I/O)		PIO (Parallel I/O)
			PIO (Parallel I/O) Intel FPGA IP <- 19.1
	</pre>		</pre>
	* Configure it with these options:		* Configure it with these options:

FabienM: /* UniPHY controller */

2019-11-12T13:06:26Z

UniPHY controller

← Older revision		Revision as of 15:06, 12 November 2019
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	Memory Interfaces with UniPHY		Memory Interfaces with UniPHY
	DDR3 SDRAM Controller with UniPHY		DDR3 SDRAM Controller with UniPHY
			DDR3 SDRAM Controller with UniPHY Intel FPGA IP <- 19.1
	</pre>		</pre>

FabienM: /* Adding the PCIe and CvP */

2019-11-12T13:03:53Z

Adding the PCIe and CvP

← Older revision		Revision as of 15:03, 12 November 2019
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	Transceiver PHY		Transceiver PHY
	Transceiver Reconfiguration Controller		Transceiver Reconfiguration Controller
			Transceiver Reconfiguration Controller Intel FPGA IP <- 19.1
	</pre>		</pre>
	* Connect previous PCIe IP signals with:		* Connect previous PCIe IP signals with:

FabienM: /* Adding the PCIe and CvP */

2019-11-12T13:02:34Z

Adding the PCIe and CvP

← Older revision		Revision as of 15:02, 12 November 2019
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	PCI Express		PCI Express
	Altera PCIe Reconfig Driver		Altera PCIe Reconfig Driver
			Altera PCIe Reconfig Driver Intel FPGA IP <- 19.1
	</pre>		</pre>
	* Connect previous IP signals with:		* Connect previous IP signals with:

FabienM at 12:59, 12 November 2019

2019-11-12T12:59:12Z

← Older revision		Revision as of 14:59, 12 November 2019
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	This howto is designed for :		This howto is designed for :
	* [[APF6_SP\|APF6D_SP-M1GE4G-4m-BW-C4M384]]: APF6_SP Dual with CycloneV C4 (speed C8) and two DDR3 chips		* [[APF6_SP\|APF6D_SP-M1GE4G-4m-BW-C4M384]]: APF6_SP Dual with CycloneV C4 (speed C8) and two DDR3 chips
	* '''Quartus 17.0.0''' : Quartus 17 without update		* Quartus with following versions:
			** '''Quartus 17.0.0''' : Quartus 17 without update
			** '''Quartus 19.1''' : Quartus Intel version
	** To install Quartus see [[Quartus_installation_on_Linux \| this page]].		** To install Quartus see [[Quartus_installation_on_Linux \| this page]].

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	= Make the Qsys project =		= Make the Qsys project =

	* Open Qsys: '''Tools'''->'''Qsys'''		* Open Qsys/Platform designer:
			** With Quartus 17: '''Tools'''->'''Qsys'''
			** With Quartus 19.1: '''Tools'''->'''Platform designer'''
	* Delete the component '''clk_0''' then save the Qsys project as : '''qsys_tfht.qsys'''		* Delete the component '''clk_0''' then save the Qsys project as : '''qsys_tfht.qsys'''
	* Click on '''Finish''' and generate the component with all options left by default		* Click on '''Finish''' and generate the component with all options left by default
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	Interface Protocols		Interface Protocols
	PCI Express		PCI Express
	Avalon-MM Cyclone V Hard IP for PCI Express		Avalon-MM Cyclone V Hard IP for PCI Express
			Avalon-MM Cyclone V Hard IP for PCI Express Intel FPGA IP <- 19.1
	</pre>		</pre>
	* "Add" it to design.		* "Add" it to design.

FabienM at 09:34, 5 November 2019

2019-11-05T09:34:58Z

← Older revision		Revision as of 11:34, 5 November 2019
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	This howto is designed for :		This howto is designed for :
	* [[APF6_SP\|APF6D_SP-M1GE4G-4m-BW-C4M384]]: APF6_SP Dual with CycloneV C4 (speed C8) and two DDR3 chips		* [[APF6_SP\|APF6D_SP-M1GE4G-4m-BW-C4M384]]: APF6_SP Dual with CycloneV C4 (speed C8) and two DDR3 chips
	* '''Quartus 15.1.1''' : Quartus ~~15 with~~ update 1		* '''Quartus 17.0.0''' : Quartus 17 without update
	** To install Quartus 15 see [[Quartus_installation_on_Linux~~#Version_15.1_prime_lite~~ \| this page]].		** To install Quartus see [[Quartus_installation_on_Linux \| this page]].

	[[File:APF6_SP_full_howto.png\|frame\|center\|The full design for this howto]]		[[File:APF6_SP_full_howto.png\|frame\|center\|The full design for this howto]]
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	* click on "Finish"		* click on "Finish"
	* Export these signals with name in '''bold''' (right click in "Hierarchy", then choose "Connections" and "Export as:...":		* Export these signals with name in '''bold''' (right click in "Hierarchy", then choose "Connections" and "Export as:..."). Exported signals will be accessible on top of module:
	** refclk : '''refclk'''		** refclk : '''refclk'''
	** npor: '''npor'''		** npor: '''npor'''
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	** '''coreclkout''' -> '''mgmt_clk_clk'''		** '''coreclkout''' -> '''mgmt_clk_clk'''
	** '''nreset_status''' -> '''mgmt_rst_reset'''		** '''nreset_status''' -> '''mgmt_rst_reset'''
	** '''reconfig_mgmt''' -> '''reconfig_mgmt'''		** reconfig_driver.'''reconfig_mgmt''' -> '''reconfig_mgmt'''
	** reconfig_driver.'''reconfig_busy''' -> '''reconfig_busy'''		** reconfig_driver.'''reconfig_busy''' -> '''reconfig_busy'''
	** pci.'''reconfig_to_xcvr''' -> '''reconfig_to_xcvr'''		** pci.'''reconfig_to_xcvr''' -> '''reconfig_to_xcvr'''
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	*** Change base address of cntl to '''0x0000_4000'''		*** Change base address of cntl to '''0x0000_4000'''
	** '''Rxm_BAR1''' -> '''windowed_slave'''		** '''Rxm_BAR1''' -> '''windowed_slave'''
	* And ~~foolowing~~ extender signals to DDR3 one:		* And following extender signals to DDR3 one:
	** '''expanded_master''' -> '''avl_0'''		** '''expanded_master''' -> mem_if_ddr3_emif_0.'''avl_0'''

	== Adding the button and LED (PIO) ==		== Adding the button and LED (PIO) ==
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	* PCIe		* PCIe
	** Outside Quartus, create a file named '''pcie_pinout.tcl'' and edit it with your favorite text editor ~~(vim ;-) )~~.		** Outside Quartus, create a file named '''pcie_pinout.tcl'' and edit it with your favorite text editor.
	** Copy all lines from [[APF6_SP_DDR3_PINOUT#PCIe\| here]].		** Copy all lines from [[APF6_SP_DDR3_PINOUT#PCIe\| here]].
	** Save your file, then add it to the project inside Quartus		** Save your file, then add it to the project inside Quartus
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	</pre>		</pre>
	* DDR3		* DDR3
	** Create a file named '''ddr3_pinout.tcl'' and edit it.		** Create a file named '''ddr3_pinout.tcl''' and edit it.
	** Copy all lines from [[APF6_SP_DDR3_PINOUT#DDR3\| here]] ('''Pinout placement''' and '''Technology pinout''').		** Copy all lines from [[APF6_SP_DDR3_PINOUT#DDR3\| here]] ('''Pinout placement''' and '''Technology pinout''').
	** Save then add the file to project		** Save then add the file to project
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	$ find . -name "*_p0_pin_map.tcl" \| xargs sed -iolt "/_mem_if_ddr3_emif_0_p0_get_input_clk_id {/a return \$pll_output_node_id"		$ find . -name "*_p0_pin_map.tcl" \| xargs sed -iolt "/_mem_if_ddr3_emif_0_p0_get_input_clk_id {/a return \$pll_output_node_id"
	</pre>		</pre>
	{{Note\| ~~Each~~ time synthesis is relaunched, this shell line must be relaunch}}		{{Note\| This is the [[DDR3-CycloneV_interface_description#The_DDR3_clock_hack \| DDR3 clock hack]], each time synthesis is relaunched, this shell line must be relaunch}}
	* Right click on ''Assembler (Generate programming files)'' then '''Start'''		* Right click on ''Assembler (Generate programming files)'' then '''Start'''
	* Convert bitstream to rbf with menu:		* Convert bitstream to rbf with menu:
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	[*] pcidebug		[*] pcidebug
	</pre>		</pre>
			{{Note \| On current Armadeus BSP, pcidebug is already installed by default}}
	* Then make the binaries and [[Target_Software_Installation \|flash it]] on the apf6_sp.		* Then make the binaries and [[Target_Software_Installation \|flash it]] on the apf6_sp.
	* Adding the rbf file to your [[Communicate_with_your_board_from_a_Linux_Host_(Basics)#TFTP_server \| tftpboot]] directory.		* Adding the rbf file to your [[Communicate_with_your_board_from_a_Linux_Host_(Basics)#TFTP_server \| tftpboot]] directory.
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	</pre>		</pre>

	* Quit ~~then reconnect pci_debug to change for bar1~~:		* Quit:
	<pre class="apf">		<pre class="apf">
	PCI> quit		PCI> quit
			</pre>
			* then reconnect pci_debug to change for bar1:
			<pre class="apf">
	$ pci_debug -s 01:00.0 -b1		$ pci_debug -s 01:00.0 -b1
	</pre>		</pre>

FabienM: /* Synthesis, Place & route */

2017-02-10T12:25:18Z

Synthesis, Place & route

← Older revision		Revision as of 14:25, 10 February 2017
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	</pre>		</pre>

	{{Note\| These bitstreams can be found under armadeus distribution in directory `firmware/tfht/bitstreams` }}}		{{Note\| These bitstreams can be found under armadeus distribution in directory `firmware/tfht/bitstreams` }}

	= Linux BSP configuration =		= Linux BSP configuration =

FabienM: /* Linux BSP configuration */

2017-02-10T12:24:55Z

Linux BSP configuration

← Older revision		Revision as of 14:24, 10 February 2017
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	tmp/apf6_the_full_howto/output_files/tfht.periph.rbf		tmp/apf6_the_full_howto/output_files/tfht.periph.rbf
	</pre>		</pre>

			{{Note\| These bitstreams can be found under armadeus distribution in directory `firmware/tfht/bitstreams` }}}

	= Linux BSP configuration =		= Linux BSP configuration =

FabienM: /* Generate bitstream with Quartus */

2017-02-10T10:21:05Z

Generate bitstream with Quartus

← Older revision		Revision as of 12:21, 10 February 2017
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	* DDR3		* DDR3
	** Create a file named '''ddr3_pinout.tcl'' and edit it.		** Create a file named '''ddr3_pinout.tcl'' and edit it.
	** Copy all lines from [[APF6_SP_DDR3_PINOUT#DDR3\| here]] (Pinout placement '''and''' Technology pinout).		** Copy all lines from [[APF6_SP_DDR3_PINOUT#DDR3\| here]] ('''Pinout placement''' and '''Technology pinout''').
	** Save then add the file to project		** Save then add the file to project
	** Run the script with following menu, select it then '''run''':		** Run the script with following menu, select it then '''run''':