KevinJ: Created page with "Category: APF6_SP Category: FPGA === Quartus configuration === Your design must include the PCIe and CvP components. Once the project synthesized, open the menu:

 File -> Convert Programming Files ...

* In '''Output programming file''' select the '''programming file type:''' Raw Binary File (.rbf). * In '..."

2025-10-03T13:35:41Z

Created page with "Category: APF6_SP Category: FPGA === Quartus configuration === Your design must include the PCIe and CvP components. Once the project synthesized, open the menu: <pre class="config"> File -> Convert Programming Files ... </pre> * In '''Output programming file''' select the '''programming file type:''' Raw Binary File (.rbf). * In '..."

New page

[[Category: APF6_SP]]
[[Category: FPGA]]

=== Quartus configuration ===

Your design must include the [[IMX6-CycloneV_interface_description#Qsys_.28Quartus.29_:_Avalon-MM_Cyclone_V_Hard_IP_for_PCI_Express_configuration_.28CvP.29 | PCIe and CvP components]]. Once the project synthesized, open the menu:
<pre class="config">
File -> Convert Programming Files ...
</pre>

* In '''Output programming file''' select the '''programming file type:''' Raw Binary File (.rbf).
* In '''Input files to convert''' clic on '''Add Files...''' and add your binary.sof file.
* In '''Output programming file''' check the option Create CvP files (Generate binary.periph.rbf and binary.core.rbf)
* Click on '''Generate'''

You will get two files:

* '''binary.periph.rbf''': peripheral config file to be loaded via serial config bus with U-Boot
* '''binary.core.rbf''': core config file to be loaded via PCIe bus with Linux.

APF6 SP FPGA designing - Revision history