APF51 FPGA-IMX interface description - Revision history

FabienM: /* Hardware */

2011-03-15T16:37:09Z

Hardware

← Older revision		Revision as of 18:37, 15 March 2011
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	* '''CLK0''': General clock for FPGA, generated by the i.MX51		* '''CLK0''': General clock for FPGA, generated by the i.MX51
	* '''OE''': Read signal		* '''OE''': Read signal
	* '''RW''': Write signal		* '''RW''': Read/Write signal
	* '''DTACK''': used as a data ack. signal for single async. accesses.		* '''DTACK''': used as a data ack. signal for single async. accesses.
	* '''WAIT''': For burst mode, asserted when slave is busy.		* '''WAIT''': For burst mode, asserted when slave is busy.

2011-03-15T16:01:10Z

Hardware

← Older revision		Revision as of 18:01, 15 March 2011
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	* '''DTACK''': used as a data ack. signal for single async. accesses.		* '''DTACK''': used as a data ack. signal for single async. accesses.
	* '''WAIT''': For burst mode, asserted when slave is busy.		* '''WAIT''': For burst mode, asserted when slave is busy.


	~~Mapping :~~
	* CS1 -> B800_0000
	* CS2 -> C000_0000

2011-03-15T16:00:41Z

Hardware

← Older revision		Revision as of 18:00, 15 March 2011
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	* '''BCLK''': bus clock.		* '''BCLK''': bus clock.
	* '''EB[2]''': Those active-low output signals indicate active data bytes for the current		* '''EB[2]''': Those active-low output signals indicate active data bytes for the current access. They may be configured to assert for write cycles only.
	access. They may be configured to assert for write cycles only.
	* '''CS2''': Chip select 1 corresponding to address B800_0000		* '''CS2''': Chip select 1 corresponding to address B800_0000
	* '''CS1''': Chip select 2 corresponding to address C000_0000		* '''CS1''': Chip select 2 corresponding to address C000_0000

2011-03-15T15:55:23Z

Hardware

← Older revision		Revision as of 17:55, 15 March 2011
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	* '''BCLK''': bus clock.		* '''BCLK''': bus clock.
	* '''EB[2]''':		* '''EB[2]''': Those active-low output signals indicate active data bytes for the current
			access. They may be configured to assert for write cycles only.
	* '''CS2''': Chip select 1 corresponding to address B800_0000		* '''CS2''': Chip select 1 corresponding to address B800_0000
	* '''CS1''': Chip select 2 corresponding to address C000_0000		* '''CS1''': Chip select 2 corresponding to address C000_0000

2011-03-15T15:27:52Z

Hardware

← Older revision		Revision as of 17:27, 15 March 2011
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	* '''BCLK''': bus clock.		* '''BCLK''': bus clock.
	* '''EB[2]''':		* '''EB[2]''':
	* '''CS2''': Chip select 1 corresponding to address B800_0000		* '''CS2''': Chip select 1 corresponding to address B800_0000
	* '''CS1''': Chip select 2 corresponding to address C000_0000		* '''CS1''': Chip select 2 corresponding to address C000_0000
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	* '''RW''': Write signal		* '''RW''': Write signal
	* '''DTACK''': used as a data ack. signal for single async. accesses.		* '''DTACK''': used as a data ack. signal for single async. accesses.
	* '''WAIT''': For burst mode, when slave is busy.		* '''WAIT''': For burst mode, asserted when slave is busy.

2011-03-15T15:13:08Z

Hardware

← Older revision		Revision as of 17:13, 15 March 2011
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	* '''BCLK''': bus clock.		* '''BCLK''': bus clock.
	* '''EB[2]''':		* '''EB[2]''':
	* '''CS2''':		* '''CS2''': Chip select 1 corresponding to address B800_0000
	* '''CS1''':		* '''CS1''': Chip select 2 corresponding to address C000_0000
	* '''LBA''': Noted ''ADV'' in reference manual.		* '''LBA''': Noted ''ADV'' in reference manual.
	* '''DA[16]''': Address/Data multiplexed bus.		* '''DA[16]''': Address/Data multiplexed bus.
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	* '''OE''': Read signal		* '''OE''': Read signal
	* '''RW''': Write signal		* '''RW''': Write signal
	* '''DTACK''':		* '''DTACK''': used as a data ack. signal for single async. accesses.
	* '''WAIT''':		* '''WAIT''': For burst mode, when slave is busy.

2010-12-16T08:49:56Z

← Older revision		Revision as of 10:49, 16 December 2010
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	{{Under_Construction}}		{{Under_Construction}}

	This article describe the interface between ~~IMX~~ and Spartan6 on APF51.		This article describe the interface between the i.MX51 and the Spartan6 on [[APF51]].
	Documentation of i.MX interface can be found in the ~~iMX~~ reference manual, chapter 63,		Documentation of i.MX interface can be found in the i.MX reference manual, chapter 63, «Wireless External Interface Module ('''WEIM''')».
	«Wireless External Interface Module ('''WEIM''')».

	== Hardware ==		== Hardware ==

	The detailed electronic schematics of ~~apf51 fpga~~ interface can be found on		The detailed electronic schematics of [[APF51]] FPGA interface can be found on [http://www.armadeus.com/_downloads/apf51/hardware/apf51.pdf this document] page 15.
	[http://www.armadeus.com/_downloads/apf51/hardware/apf51.pdf this document] page 15.

	Signals used in the design are:		Signals used in the design are:

2010-12-15T14:33:49Z

Hardware

← Older revision		Revision as of 16:33, 15 December 2010
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	* '''BCLK''': bus clock.		* '''BCLK''': bus clock.
	* '''EB[2]''':		* '''EB[2]''':
	* '''~~CS0~~''':		* '''CS2''':
	* '''CS1''':		* '''CS1''':
	* '''LBA''': Noted ''ADV'' in reference manual.		* '''LBA''': Noted ''ADV'' in reference manual.

2010-12-15T13:46:37Z

Hardware

2010-12-15T09:20:13Z

← Older revision		Revision as of 11:20, 15 December 2010
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	Documentation of i.MX interface can be found in the iMX reference manual, chapter 63,		Documentation of i.MX interface can be found in the iMX reference manual, chapter 63,
	«Wireless External Interface Module ('''WEIM''')».		«Wireless External Interface Module ('''WEIM''')».

			== Hardware ==

			The detailed electronic schematics of apf51 fpga interface can be found on
			[http://www.armadeus.com/_downloads/apf51/hardware/apf51.pdf this document] page 15.

			Signals used in the design are:

			* '''BCLK''': bus clock.
			* '''EB[2]''':
			* '''CS0''':
			* '''CS1''':
			* '''LBA''': Noted ''ADV'' in reference manual.
			* '''DA[16]''': Address/Data multiplexed bus.
			* '''CLK0''': General clock for FPGA, generated by the i.MX51
			* '''OE''': Read signal
			* '''RW''': Write signal
			* '''DTACK''':
			* '''WAIT''':