APF27 FPGA-IMX interface description - Revision history

FabienM at 10:47, 10 December 2019

2019-12-10T10:47:58Z

← Older revision		Revision as of 11:47, 10 December 2019
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	~~{{Under_Construction}}~~

	This article describe the interface between IMX and Spartan3A on APF27.		This article describe the interface between IMX and Spartan3A on APF27.

FabienM: /* Synchronous access with FPGA at 100MHz default configuration on APF27 */

2011-08-22T07:27:59Z

Synchronous access with FPGA at 100MHz default configuration on APF27

← Older revision		Revision as of 08:27, 22 August 2011
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	[[image:dtack.png\|center\|500px\|thumb\|'''figure 3''' - ''Read access using dtack'']]		[[image:dtack.png\|center\|500px\|thumb\|'''figure 3''' - ''Read access using dtack'']]

	=== Synchronous access with FPGA at 100MHz ''default configuration on APF27''===		=== Synchronous access with FPGA at 100MHz ''(default configuration on APF27)''===

	The main problem with fpga clocked at 100MHz is that wishbone will not be synchronous with WEIM interface (clocked at 133MHz).		The main problem with fpga clocked at 100MHz is that wishbone will not be synchronous with WEIM interface (clocked at 133MHz).

FabienM: /* Simulation */

2011-08-22T07:27:39Z

Simulation

← Older revision		Revision as of 08:27, 22 August 2011
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	==== Simulation ====		==== Simulation ====

	To unsure that interface work well, we will simulate it~~. To reproduce this simulation, ask [[User:FabienM]] that will give you the project (~/podtree/trunk/src/tests/testbus)~~.		To unsure that interface work well, we will simulate it.

	[[image:static_fpga100.jpg\|center\|500px\|thumb\|'''figure 4''' - ''Timings simulation with FPGA clock at 100MHz, with WSC=6'']]		[[image:static_fpga100.jpg\|center\|500px\|thumb\|'''figure 4''' - ''Timings simulation with FPGA clock at 100MHz, with WSC=6'']]

FabienM: /* Registers configuration */

2011-01-27T11:01:14Z

Registers configuration

← Older revision		Revision as of 12:01, 27 January 2011
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	To change CLK0 to 100MHz, we will use HCLK Source (400MHz) divided by 4.		To change CLK0 to 100MHz, we will use HCLK Source (400MHz) divided by 4.

	Selecting HCLK (CCSR)		Selecting HCLK Source (CCSR)
	<pre class="apf">		<pre class="apf">
	mw 10027028 00008305 # HCLK Source (MPLL 2x clock output / 3) := 400MHz		mw 10027028 00008305 # HCLK Source (MPLL 2x clock output / 3) := 400MHz

FabienM: /* Registers configuration */

2011-01-27T11:00:41Z

Registers configuration

← Older revision		Revision as of 12:00, 27 January 2011
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	''Changing CLK0 to 100MHz:''		''Changing CLK0 to 100MHz:''

	To change CLK0 to 100MHz, we will use HCLK (400MHz) divided by 4.		To change CLK0 to 100MHz, we will use HCLK Source (400MHz) divided by 4.

	Selecting HCLK (CCSR)		Selecting HCLK (CCSR)

FabienM at 09:57, 15 December 2010

2010-12-15T09:57:03Z

← Older revision		Revision as of 10:57, 15 December 2010
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	Each chip select has its own configuration (timing, address range, ...) that can be used for different slaves in the FPGA.		Each chip select has its own configuration (timing, address range, ...) that can be used for different slaves in the FPGA.

	'''CLKO''' is ~~know~~ configured at 100MHz by default configured to simplify FPGA		'''CLKO''' is now configured at 100MHz by default configured to simplify FPGA
	IP design.		IP design.

FabienM: /* Old configuration (133MHz) */

2010-10-28T09:52:12Z

Old configuration (133MHz)

← Older revision		Revision as of 10:52, 28 October 2010
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	===Old configuration (133MHz)===		===Old configuration (133MHz)===
	The ~~default~~ configuration uses '''CS5''' for accessing the FPGA. 32 bits register CS5		The old configuration uses '''CS5''' for accessing the FPGA. 32 bits register CS5
	is used to configure all timing for this chip select. It's ~~default~~		is used to configure all timing for this chip select. It's old
	configuration '''was''' :		configuration '''was''' :
	* CS5U (Upper 16bits, see page 521 of reference manual ): mw D8002050 00000600		* CS5U (Upper 16bits, see page 521 of reference manual ): mw D8002050 00000600
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	[[image:timingstatic.png\|center\|500px\|thumb\|'''figure 2''' - ''Static timings chronograms'']]		[[image:timingstatic.png\|center\|500px\|thumb\|'''figure 2''' - ''Static timings chronograms'']]

	With this configuration, the access time (read/write) to the FPGA is set to 44ns.		With this configuration, the access time (read/write) to the FPGA was set to 44ns.

	This configuration is interesting because all timings are under control. But		This configuration was interesting because all timings are under control. But
	the problem is that to be perfectly synchronous, the FPGA is clocked at 133MHz		the problem was that to be perfectly synchronous, the FPGA was clocked at 133MHz
	like WEIM and some IP design doesn't work at this frequency.		like WEIM and some IP design doesn't work at this frequency.

FabienM at 17:42, 21 January 2010

2010-01-21T17:42:32Z

← Older revision		Revision as of 18:42, 21 January 2010
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	[[image:fpgaimx_wire.png\|center\|500px\|thumb\|'''figure 1''' - ''FPGA-i.MXL wiring'']]		[[image:fpgaimx_wire.png\|center\|500px\|thumb\|'''figure 1''' - ''FPGA-i.MXL wiring'']]

	~~The signals~~ used in the design are:		Signals used in the design are:

	* '''CLKO''': Clock generated by i.MX. Used as general clock by the FPGA.		* '''CLKO''': Clock generated by i.MX. Used as general clock by the FPGA.
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	Each chip select has its own configuration (timing, address range, ...) that can be used for different slaves in the FPGA.		Each chip select has its own configuration (timing, address range, ...) that can be used for different slaves in the FPGA.

	'''CLKO''' is by default configured to ~~run at 133MHz to be synchronous with the '''WEIM''' bus that is internally clocked at 133MHz, too~~.		'''CLKO''' is know configured at 100MHz by default configured to simplify FPGA
			IP design.

	== Chip Select Timings configuration ==		== Chip Select Timings configuration ==

	===~~Present~~ configuration (~~static timing~~)===		===Old configuration (133MHz)===
	The default configuration uses '''CS5''' for accessing the FPGA. 32 bits register CS5		The default configuration uses '''CS5''' for accessing the FPGA. 32 bits register CS5
	is used to configure all timing for this chip select. It's default		is used to configure all timing for this chip select. It's default
	configuration is:		configuration '''was''' :
	* CS5U (Upper 16bits, see page 521 of reference manual ): mw D8002050 00000600		* CS5U (Upper 16bits, see page 521 of reference manual ): mw D8002050 00000600
	This will add 6 waits state on access to read value correctly (WSC: Wait		This will add 6 waits state on access to read value correctly (WSC: Wait
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	[[image:dtack.png\|center\|500px\|thumb\|'''figure 3''' - ''Read access using dtack'']]		[[image:dtack.png\|center\|500px\|thumb\|'''figure 3''' - ''Read access using dtack'']]

	=== Synchronous access with FPGA at 100MHz ===		=== Synchronous access with FPGA at 100MHz ''default configuration on APF27''===

	The main problem with fpga clocked at 100MHz is that wishbone will not be synchronous with WEIM interface (clocked at 133MHz).		The main problem with fpga clocked at 100MHz is that wishbone will not be synchronous with WEIM interface (clocked at 133MHz).

FabienM: /* Linux testing program */

2010-01-07T17:05:07Z

Linux testing program

← Older revision		Revision as of 18:05, 7 January 2010
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	= Linux testing program =		= Linux testing program =

			A program is available for testing imx-fpga communication speed in armadeus tree in [http://armadeus.git.sourceforge.net/git/gitweb.cgi?p=armadeus/armadeus;a=tree;f=target/linux/debug/imx-fpga-test;h=c9582b3e2b47cff36cbc2aeab610f6c79f0919b3;hb=HEAD target/linux/debug/imx-fpga-test.]

FabienM at 12:37, 7 January 2010

2010-01-07T12:37:58Z

← Older revision		Revision as of 13:37, 7 January 2010
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	And is saved in armadeus tree at		And is saved in armadeus tree at
	''buildroot/target/device/armadeus/apf27/apf27.h		''buildroot/target/device/armadeus/apf27/apf27.h

			= Linux testing program =