OPOSA5E SP Interface description

FabienM — Fri, 30 Oct 2026 09:10:44 GMT

Interfaces

@@ Line 7: / Line 7: @@
 == Introduction ==
-[[File:oposa5e_sp_agilex5_bridges.jpg|caption]]
+The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone.
 There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5
-* FPGA-to-HPS (F2H) bridge
+* FPGA-to-HPS (F2H) : 256b ACE5-Lite
-* HPS-to-FPGA (H2F) bridge
+* HPS-to-FPGA (H2F) : 32/64/128 bits AXI4 interface
-* Lightweight HPS-to-FPGA (LWH2F) bridge
+* Lightweight HPS-to-FPGA (LWH2F) : 32 bits AXI4 interface
-* FPGA-to-SDRAM (F2SDRAM) bridge
+* FPGA-to-SDRAM (F2SDRAM) : 256b/128b/64b AXI-4
 The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website]
 [[Using_FPGA| << FPGA general page]]

File:Oposa5e sp agilex5 bridges.jpg

FabienM — Fri, 30 Oct 2026 08:28:44 GMT

New page

FabienM — Fri, 30 Oct 2026 08:26:14 GMT

New page

FabienM — Fri, 30 Oct 2026 08:23:38 GMT

New page

FabienM — Fri, 30 Oct 2026 08:23:23 GMT

Introduction

← Older revision		Revision as of 09:23, 30 October 2026
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	[[Category: Agilex5]]		[[Category: Agilex5]]
	[[Category: FPGA]]		[[Category: FPGA]]



	== Introduction ==		== Introduction ==

			[[File:oposa5e_sp_agilex5_bridges.jpg\|caption]]


			There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5

			* FPGA-to-HPS (F2H) bridge
			* HPS-to-FPGA (H2F) bridge
			* Lightweight HPS-to-FPGA (LWH2F) bridge
			* FPGA-to-SDRAM (F2SDRAM) bridge

			The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website]

	[[Using_FPGA\| << FPGA general page]]		[[Using_FPGA\| << FPGA general page]]