ArmadeusWiki - User contributions [en]

OPOS93 SP Interfaces description

2026-04-30T09:17:17Z

KevinJ:

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Introduction ==

The Trion T20 FPGA is accessed by the iMX93 SoC by using a custom FlexIO bus called '''FlexIO Armabus'''.

[[File:Opos93_SP_soc_fpga_diagram.png|frame|center| SoC and FPGA interface diagram for Opos93_SP]]

== FlexIO Armabus ==

The '''FlexIO Armabus''' is using FlexIO lines to design a custom 8b parallel communication bus. It consists of the following signals:
* '''clk''': Clock of the bus. Data is shifted out on rising edge and latched on falling edge.
* '''add_select''': Address select, next byte is an address byte.
* '''data_select''': Data select, next byte is a data byte.
* '''write_enable''': Write enable, 1 to write, 0 to read.
* '''data''': Bi-directionnal 8b data.

The memory space mapped on the bus is 16 bits wide.
Read/write access are done on 32b (hence 4x 8b transfer).

=== Read example ===

The following picture depicts a 32 bits read of the word 0xCAFEBABE at address 0x0042.

[[File:flexio_armabus_read32_example.png|frame|center| FlexIO Armabus 32b read]]

=== Write example ===

The following picture depicts a 32 bits write of the word 0xDEADBEEF at address 0x1545.

[[File:flexio_armabus_write32_example.png|frame|center| FlexIO Armabus 32b write]]

=== Address auto-increment mode ===

Address is automatically incremented after each fourth byte transferred.
The following chronogram depicts a write of the words 0xDEADBEEF, 0xCAFEBABE, 0xFEEDBEBE at 0x0102, 0x0103, 0x0104 respectively.

[[File:flexio_armabus_burstwrite_example.png|frame|center| FlexIO Armabus 3x32b write]]

=== Burst mode ===

Burst mode allow a much faster read than standard read mode by anticipating the data to set on the FlexIO Armabus lines.
To initiate a burst read, the '''add_select''' and the '''data_select''' signal should be set at the same time.
The '''write_enable''' signal should be set too during the first 2 transactions in order to write the size to read.
Then, the '''write_enable''' should be low until the end of the transfer.
Finally, the data are provided on the bus.
Please note that the number of clock cycles during the read phase must match the size set earlier.

The following chronogram depicts a burst read of 3 32-bits words at address 0x0023.

[[File:flexio_armabus_burstread_example.png|frame|center| FlexIO Armabus 3x32b burst read]]

[[Using_FPGA| << FPGA general page]]

File:Flexio armabus burstread example.png

2026-04-30T09:13:46Z

KevinJ:

FPGA registers access from Linux kernel on OPOS93 SP

2025-10-09T16:30:54Z

KevinJ: Created page with "Category:FPGA Category: OPOS93_SP == Introduction == Users should be able to develop their own Linux driver for their custom IPs through ''FlexIO Armabus''. == gpio-flexio-armabus example Linux driver == You can find an example driver in your Linux build repository under ''drivers/gpio/gpio-flexio-armabus.c''"

[[Category:FPGA]]
[[Category: OPOS93_SP]]

== Introduction ==

Users should be able to develop their own Linux driver for their custom IPs through ''FlexIO Armabus''.

== gpio-flexio-armabus example Linux driver ==

You can find an example driver in your Linux build repository under ''drivers/gpio/gpio-flexio-armabus.c''

File:Opos93 SP soc fpga diagram.png

2025-10-09T16:09:27Z

KevinJ: KevinJ uploaded a new version of File:Opos93 SP soc fpga diagram.png

FPGA registers access from Linux userspace on OPOS93 SP

2025-10-09T16:02:40Z

KevinJ: /* Setting address */

[[Category:FPGA]]
[[Category: OPOS93_SP]]

== Introduction ==

The ''flexio_armabus'' kernel driver is mapping the FPGA address space in a file ''/dev/armabus''. For further informations, see [[OPOS93_SP Interfaces description]].

== Setting address ==

Address should be set using the ''lseek()'' C function on the ''/dev/armabus'' file.

<source lang="c">
int fd = open("/dev/armabus", O_RDWR);
lseek(fd, 8, SEEK_SET); // Set address to 0x0008
</source>

== Read/write ==

Access to the bus should be done using ''read()'' and ''write()'' functions.
Write or read size should be multiple of 4.

<source lang="c">
write(fd, buf, 8); // Write 2 words of 32b
</source>

<source lang="c">
read(fd, buf, 4); // Read 1 word of 32b
</source>

FPGA registers access from Linux userspace on OPOS93 SP

2025-10-09T16:01:15Z

KevinJ: /* Setting address */

[[Category:FPGA]]
[[Category: OPOS93_SP]]

== Introduction ==

The ''flexio_armabus'' kernel driver is mapping the FPGA address space in a file ''/dev/armabus''. For further informations, see [[OPOS93_SP Interfaces description]].

== Setting address ==

Address should be set using the ''lseek()'' C function on the ''/dev/armabus'' file.

<source lang="c">
int fd = open("/dev/armabus", O_RDWR);
lseek(fd, 8, SEEK_SET); // Set address to 0x0008
close(fd);
</source>

== Read/write ==

Access to the bus should be done using ''read()'' and ''write()'' functions.
Write or read size should be multiple of 4.

<source lang="c">
write(fd, buf, 8); // Write 2 words of 32b
</source>

<source lang="c">
read(fd, buf, 4); // Read 1 word of 32b
</source>

OPOS93 SP Interfaces description

2025-10-09T15:56:07Z

KevinJ: /* Burst mode */

FPGA registers access from Linux userspace on OPOS93 SP

2025-10-09T15:47:57Z

KevinJ: /* Setting address */

[[Category:FPGA]]
[[Category: OPOS93_SP]]

== Introduction ==

The ''flexio_armabus'' kernel driver is mapping the FPGA address space in a file ''/dev/armabus''. For further informations, see [[OPOS93_SP Interfaces description]].

== Setting address ==

Address should be set using the ''lseek()'' C function on the ''/dev/armabus'' file.
Keep in mind that offset should be multiple of 4 because FlexIO is doing 32b access.

<source lang="c">
int fd = open("/dev/armabus", O_RDWR);
lseek(fd, 8, SEEK_SET); // Set address to 0x0008
close(fd);
</source>

== Read/write ==

Access to the bus should be done using ''read()'' and ''write()'' functions.
Write or read size should be multiple of 4.

<source lang="c">
write(fd, buf, 8); // Write 2 words of 32b
</source>

<source lang="c">
read(fd, buf, 4); // Read 1 word of 32b
</source>

FPGA registers access from Linux userspace on OPOS93 SP

2025-10-09T15:45:27Z

KevinJ:

[[Category:FPGA]]
[[Category: OPOS93_SP]]

== Introduction ==

The ''flexio_armabus'' kernel driver is mapping the FPGA address space in a file ''/dev/armabus''. For further informations, see [[OPOS93_SP Interfaces description]].

== Setting address ==

Address should be set using the ''lseek()'' C function on the ''/dev/armabus'' file.
Keep in mind that offset should be multiple of 4 because FlexIO is doing 32b access.

<source lang="c">
int fd = open("/dev/armabus", O_RDWR);
lseek(fd, 8, SEEK_SET); // Set address to 0x0002
close(fd);
</source>

== Read/write ==

Access to the bus should be done using ''read()'' and ''write()'' functions.
Write or read size should be multiple of 4.

<source lang="c">
write(fd, buf, 8); // Write 2 words of 32b
</source>

<source lang="c">
read(fd, buf, 4); // Read 1 word of 32b
</source>

Using FPGA

2025-10-09T15:31:11Z

KevinJ: /* Developing on the APF FPGA */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

==== Accessing the FPGA address domain from Linux userspace ====
* [[FPGA_registers_access_from_Linux_userspace_on_APF9328,_APF27_SP,_APF51_SP_and_OPOS6UL_SP | APF9328, APF27_SP, APF51_SP and OPOS6UL_SP]]
* [[FPGA_registers_access_from_Linux_userspace_on_APF6_SP | APF6_SP]]
* [[FPGA_registers_access_from_Linux_userspace_on_OPOS93_SP | OPOS93_SP]]

==== Accessing the FPGA address domain from Linux kernel ====

* [[FPGA_registers_access_from_Linux_kernel_on_OPOS93_SP | OPOS93_SP]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
*'''OPOS93_SP'''
** [[OPOS93_SP_FPGA_designing | FPGA designing]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Efinix'''
* [[Efinity]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

FPGA registers access from Linux userspace on OPOS93 SP

2025-10-09T15:29:26Z

KevinJ: /* Setting address */

OPOS93 SP Interfaces description

2025-10-09T15:22:36Z

KevinJ: /* Burst mode */

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Introduction ==

The Trion T20 FPGA is accessed by the iMX93 SoC by using a custom FlexIO bus called '''FlexIO Armabus'''.

[[File:Opos93_SP_soc_fpga_diagram.png|frame|center| SoC and FPGA interface diagram for Opos93_SP]]

== FlexIO Armabus ==

The '''FlexIO Armabus''' is using FlexIO lines to design a custom 8b parallel communication bus. It consists of the following signals:
* '''clk''': Clock of the bus. Data is shifted out on rising edge and latched on falling edge.
* '''add_select''': Address select, next byte is an address byte.
* '''data_select''': Data select, next byte is a data byte.
* '''write_enable''': Write enable, 1 to write, 0 to read.
* '''data''': Bi-directionnal 8b data.

The memory space mapped on the bus is 16 bits wide.
Read/write access are done on 32b (hence 4x 8b transfer).

=== Read example ===

The following picture depicts a 32 bits read of the word 0xCAFEBABE at address 0x0042.

[[File:flexio_armabus_read32_example.png|frame|center| FlexIO Armabus 32b read]]

=== Write example ===

The following picture depicts a 32 bits write of the word 0xDEADBEEF at address 0x1545.

[[File:flexio_armabus_write32_example.png|frame|center| FlexIO Armabus 32b write]]

=== Burst mode ===

Address is automatically incremented after each fourth byte transferred.
Please note that it is the default behavior but this can be modified in the FlexIO instance module in the FPGA design.
The following chronogram depicts a burst write of the words 0xDEADBEEF, 0xCAFEBABE, 0xFEEDBEBE at 0x0102, 0x0103, 0x0104 respectively.

[[File:flexio_armabus_burstwrite_example.png|frame|center| FlexIO Armabus 3x32b burst write]]

[[Using_FPGA| << FPGA general page]]

FPGA registers access from Linux userspace on OPOS93 SP

2025-10-09T15:19:24Z

KevinJ: /* Read/write */

FPGA registers access from Linux userspace on OPOS93 SP

2025-10-09T15:18:58Z

KevinJ:

OPOS93 SP Interfaces description

2025-10-09T14:58:12Z

KevinJ:

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Introduction ==

The Trion T20 FPGA is accessed by the iMX93 SoC by using a custom FlexIO bus called '''FlexIO Armabus'''.

[[File:Opos93_SP_soc_fpga_diagram.png|frame|center| SoC and FPGA interface diagram for Opos93_SP]]

== FlexIO Armabus ==

The '''FlexIO Armabus''' is using FlexIO lines to design a custom 8b parallel communication bus. It consists of the following signals:
* '''clk''': Clock of the bus. Data is shifted out on rising edge and latched on falling edge.
* '''add_select''': Address select, next byte is an address byte.
* '''data_select''': Data select, next byte is a data byte.
* '''write_enable''': Write enable, 1 to write, 0 to read.
* '''data''': Bi-directionnal 8b data.

The memory space mapped on the bus is 16 bits wide.
Read/write access are done on 32b (hence 4x 8b transfer).

=== Read example ===

The following picture depicts a 32 bits read of the word 0xCAFEBABE at address 0x0042.

[[File:flexio_armabus_read32_example.png|frame|center| FlexIO Armabus 32b read]]

=== Write example ===

The following picture depicts a 32 bits write of the word 0xDEADBEEF at address 0x1545.

[[File:flexio_armabus_write32_example.png|frame|center| FlexIO Armabus 32b write]]

=== Burst mode ===

Address is automatically incremented after each fourth byte transferred.
Please note that it is the default behavior but this can be modified in the FlexIO instance module in the FPGA design.
The following chronogram depicts a burst write of the words 0xDEADBEEF, 0xCAFEBABE, 0xFEEDBEBE at 0x0102, 0x0103, 0x0104 respectively.

[[File:flexio_armabus_write32_example.png|frame|center| FlexIO Armabus 3x32b burst write]]

[[Using_FPGA| << FPGA general page]]

OPOS93 SP Interfaces description

2025-10-09T14:49:16Z

KevinJ:

[[Category: OPOS93_SP]]
[[Category: FPGA]]

{{Under_Construction}}

== Introduction ==

The Trion T20 FPGA is accessed by the iMX93 SoC by using a custom FlexIO bus called '''FlexIO Armabus'''.

[[File:Opos93_SP_soc_fpga_diagram.png|frame|center| SoC and FPGA interface diagram for Opos93_SP]]

== FlexIO Armabus ==

The '''FlexIO Armabus''' is using FlexIO lines to design a custom 8b parallel communication bus. It consists of the following signals:
* '''clk''': Clock of the bus. Data is shifted out on rising edge and latched on falling edge.
* '''add_select''': Address select, next byte is an address byte.
* '''data_select''': Data select, next byte is a data byte.
* '''write_enable''': Write enable, 1 to write, 0 to read.
* '''data''': Bi-directionnal 8b data.

The memory space mapped on the bus is 16 bits wide.
Read/write access are done on 32b (hence 4x 8b transfer).

=== Read example ===

The following picture depicts a 32 bits read of the word 0xCAFEBABE at address 0x0042.

[[File:flexio_armabus_read32_example.png|frame|center| FlexIO Armabus 32b read]]

=== Write example ===

The following picture depicts a 32 bits write of the word 0xDEADBEEF at address 0x1545.

[[File:flexio_armabus_write32_example.png|frame|center| FlexIO Armabus 32b write]]

=== Burst mode ===

Address is automatically incremented after each fourth byte transferred.
Please note that it is the default behavior but this can be modified in the FlexIO instance module in the FPGA design.
The following chronogram depicts a burst write of the words 0xDEADBEEF, 0xCAFEBABE, 0xFEEDBEBE at 0x0102, 0x0103, 0x0104 respectively.

[[File:flexio_armabus_write32_example.png|frame|center| FlexIO Armabus 3x32b burst write]]

[[Using_FPGA| << FPGA general page]]

File:Flexio armabus burstwrite example.png

2025-10-09T14:44:38Z

KevinJ:

File:Flexio armabus write32 example.png

2025-10-09T14:33:14Z

KevinJ:

File:Flexio armabus read32 example.png

2025-10-09T14:01:09Z

KevinJ:

OPOS93 SP Interfaces description

2025-10-09T09:48:50Z

KevinJ:

File:Opos93 SP soc fpga diagram.png

2025-10-09T09:47:29Z

KevinJ:

FPGA registers access from Linux userspace on OPOS93 SP

2025-10-09T08:39:45Z

KevinJ:

[[Category:FPGA]]
[[Category: OPOS93_SP]]

== Introduction ==

FPGA registers access from Linux userspace on OPOS93 SP

2025-10-09T08:39:14Z

KevinJ: Created page with "Category:FPGA Category: OPOS93_SP"

[[Category:FPGA]]
[[Category: OPOS93_SP]]

Using FPGA

2025-10-09T08:38:50Z

KevinJ: /* Accessing the FPGA address domain from Linux userspace */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

==== Accessing the FPGA address domain from Linux userspace ====
* [[FPGA_registers_access_from_Linux_userspace_on_APF9328,_APF27_SP,_APF51_SP_and_OPOS6UL_SP | APF9328, APF27_SP, APF51_SP and OPOS6UL_SP]]
* [[FPGA_registers_access_from_Linux_userspace_on_APF6_SP | APF6_SP]]
* [[FPGA_registers_access_from_Linux_userspace_on_OPOS93_SP | OPOS93_SP]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
*'''OPOS93_SP'''
** [[OPOS93_SP_FPGA_designing | FPGA designing]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Efinix'''
* [[Efinity]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

FPGA registers access from Linux userspace on APF9328, APF27 SP, APF51 SP and OPOS6UL SP

2025-10-09T08:33:52Z

KevinJ:

[[Category:FPGA]]
[[Category: APF9328]]
[[Category: APF27]]
[[Category: APF51]]
[[Category: OPOS6UL_SP]]

== Introduction ==

For '''APF9328, APF27, APF51 and OPOS6UL_SP''', registers access are done with a memory bus (parallel).
Access through this bus can be made by two methods:
* Using ''fpgaregs'' tool

== fpgaregs ==
===Installation===
If the fpgaregs package is not already installed on your APF (''/usr/bin/fpgaregs''), you can select it in the Buildroot menuconfig:
<pre class="host">
$ make menuconfig
</pre>

<pre class="config">
Package Selection for the target --->
[*] Hardware handling / blockdevices and filesystem maintenance --->
[*] fpgaregs
</pre>

<pre class="host">
$ make
</pre>

Then reflash your rootfs or install it manually.

===Usage===

''fpgaregs'' can be used to do read or write accesses (16 or 32 bits wide) to the FPGA, from Linux userspace/console.

====16 bits read====
<pre class="apf">
# fpgaregs w <address>
</pre>

Where <address> is an address relative to FPGA's mapping in hexadecimal value. Example:
<pre class="apf">
# fpgaregs w 0
</pre>

====16 bits write====
<pre class="apf">
# fpgaregs w <address> <value>
</pre>

Where <value> is hexadecimal value to write.

====32 bits read====
<pre class="apf">
# fpgaregs l <address>
</pre>

====32 bits write====
<pre class="apf">
# fpgaregs l <address> <value>
</pre>

== the mmap problem ==

{{Note| This problem is corrected with latest Toolchains compilation options}}

First of all, you need to get a file descriptor for ''/dev/mem'' using the ''open()'' function
<source lang="c">
ffpga=open("/dev/mem",O_RDWR|O_SYNC);
</source>
Now you have a valid file descriptor to access your FPGA.

The O_SYNC option is recommended to avoid Linux to cache the content of /dev/mem and delay any modification done in this file.

To access fpga register, fpgaregs use the ''mmap()'' system call :

<source lang="c">
void * ptr_fpga;
ptr_fpga = mmap (0, 8192, PROT_READ|PROT_WRITE, MAP_SHARED, ffpga, FPGA_ADDRESS);
</source>

Thanks to this function, fpga registers are accessible directly on memory with pointer ptr_fpga. To read and write in 16bits or in 32 bits we will cast the pointer value in ''unsigned short'' or ''unsigned int'' :

'''16bits'''
''write''
<source lang="c">
*(unsigned short*)(ptr_fpga+(address)) = (unsigned short)value;
</source>
''read''
<source lang="c">
value = *(unsigned short*)(ptr_fpga+(address));
</source>

'''32 bits'''
''write''
<source lang="c">
*(unsigned int*)(ptr_fpga+(address)) = (unsigned short)value;
</source>

''read''
<source lang="c">
value = *(unsigned int*)(ptr_fpga+(address));
</source>

=== The problem ===

By default, if the specific ''arm920t'' target is not specified, ''arm-linux-gcc'' will try to generate compatible read/write for all ARM9 model when it access register in 16bits. Indeed it seems that not all ARM9 have 16bits read/write capabilities (''ldrh'' asm instruction).

As the interface between i.MXL and FPGA on APF9328 has no 8bits read/write capabilities, each 8 bits access is recognized by the FPGA as a 16bits access. So on each 16bits access of the i.MXL, FPGA will process two 16bits access instead of 1. That is a problem when accessing a FIFO for example.

To avoid this painful problem don't forget the ''-mcpu=arm920t'' option when compiling ''fpgaregs'' for APF9328 and ''-mcpu=arm926ej-s'' for APF27.

==Links==
* http://sources.redhat.com/ml/crossgcc/2005-08/msg00120.html : Explanation of the problem.

FPGA registers access from Linux userspace on APF6 SP

2025-10-09T08:33:48Z

KevinJ: Created page with "Category:FPGA Category: APF6_SP == Introduction == For '''APF6_SP''' registers access are done with PCIe == PCIe == On APF6_SP FPGA memory is accessed with PCIe, to read/write on FPGA space an example is available with pci_debug. === Pci_debug === See pci_debug page to know how to access PCIe address space with a command line tool."

[[Category:FPGA]]
[[Category: APF6_SP]]

== Introduction ==

For '''APF6_SP''' registers access are done with PCIe

== PCIe ==

On [[APF6_SP]] FPGA memory is accessed with PCIe, to read/write on FPGA space an example is available with [[Pci_debug | pci_debug]].

=== Pci_debug ===

See [[Pci_debug | pci_debug]] page to know how to access PCIe address space with a command line tool.

Using FPGA

2025-10-09T08:27:39Z

KevinJ: /* Accessing the FPGA address domain from Linux userspace */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

==== Accessing the FPGA address domain from Linux userspace ====
* [[FPGA_registers_access_from_Linux_userspace_on_APF9328,_APF27_SP,_APF51_SP_and_OPOS6UL_SP | APF9328, APF27_SP, APF51_SP and OPOS6UL_SP]]
* [[FPGA_registers_access_from_Linux_userspace_on_APF6_SP | APF6_SP]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
*'''OPOS93_SP'''
** [[OPOS93_SP_FPGA_designing | FPGA designing]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Efinix'''
* [[Efinity]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

FPGA registers access from Linux userspace

2025-10-09T08:26:20Z

KevinJ: KevinJ moved page FPGA registers access from Linux userspace to FPGA registers access from Linux userspace on APF9328, APF27 SP, APF51 SP and OPOS6UL SP

#REDIRECT [[FPGA registers access from Linux userspace on APF9328, APF27 SP, APF51 SP and OPOS6UL SP]]

FPGA registers access from Linux userspace on APF9328, APF27 SP, APF51 SP and OPOS6UL SP

2025-10-09T08:26:20Z

KevinJ: KevinJ moved page FPGA registers access from Linux userspace to FPGA registers access from Linux userspace on APF9328, APF27 SP, APF51 SP and OPOS6UL SP

[[Category:FPGA]]

== Introduction ==

There are '''two methods''' to access FPGA registers on APF*.

* For '''APF9328, APF27 and APF51''' registers access are done with a memory bus (parallel).
* For '''APF6_SP''' registers access are done with PCIe

== Memory bus ==
=== fpgaregs ===
====Installation====
If the fpgaregs package is not already installed on your APF (''/usr/bin/fpgaregs''), you can select it in the Buildroot menuconfig:
<pre class="host">
$ make menuconfig
</pre>

<pre class="config">
Package Selection for the target --->
[*] Hardware handling / blockdevices and filesystem maintenance --->
[*] fpgaregs
</pre>

<pre class="host">
$ make
</pre>

Then reflash your rootfs or install it manually.

====Usage====

''fpgaregs'' can be used to do read or write accesses (16 or 32 bits wide) to the FPGA, from Linux userspace/console.

=====16 bits read=====
<pre class="apf">
# fpgaregs w <address>
</pre>

Where <address> is an address relative to FPGA's mapping in hexadecimal value. Example:
<pre class="apf">
# fpgaregs w 0
</pre>

=====16 bits write=====
<pre class="apf">
# fpgaregs w <address> <value>
</pre>

Where <value> is hexadecimal value to write.

=====32 bits read=====
<pre class="apf">
# fpgaregs l <address>
</pre>

=====32 bits write=====
<pre class="apf">
# fpgaregs l <address> <value>
</pre>

=== the mmap problem ===

{{Note| This problem is corrected with latest Toolchains compilation options}}

First of all, you need to get a file descriptor for ''/dev/mem'' using the ''open()'' function
<source lang="c">
ffpga=open("/dev/mem",O_RDWR|O_SYNC);
</source>
Now you have a valid file descriptor to access your FPGA.

The O_SYNC option is recommended to avoid Linux to cache the content of /dev/mem and delay any modification done in this file.

To access fpga register, fpgaregs use the ''mmap()'' system call :

<source lang="c">
void * ptr_fpga;
ptr_fpga = mmap (0, 8192, PROT_READ|PROT_WRITE, MAP_SHARED, ffpga, FPGA_ADDRESS);
</source>

Thanks to this function, fpga registers are accessible directly on memory with pointer ptr_fpga. To read and write in 16bits or in 32 bits we will cast the pointer value in ''unsigned short'' or ''unsigned int'' :

'''16bits'''
''write''
<source lang="c">
*(unsigned short*)(ptr_fpga+(address)) = (unsigned short)value;
</source>
''read''
<source lang="c">
value = *(unsigned short*)(ptr_fpga+(address));
</source>

'''32 bits'''
''write''
<source lang="c">
*(unsigned int*)(ptr_fpga+(address)) = (unsigned short)value;
</source>

''read''
<source lang="c">
value = *(unsigned int*)(ptr_fpga+(address));
</source>

==== The problem ====

By default, if the specific ''arm920t'' target is not specified, ''arm-linux-gcc'' will try to generate compatible read/write for all ARM9 model when it access register in 16bits. Indeed it seems that not all ARM9 have 16bits read/write capabilities (''ldrh'' asm instruction).

As the interface between i.MXL and FPGA on APF9328 has no 8bits read/write capabilities, each 8 bits access is recognized by the FPGA as a 16bits access. So on each 16bits access of the i.MXL, FPGA will process two 16bits access instead of 1. That is a problem when accessing a FIFO for example.

To avoid this painful problem don't forget the ''-mcpu=arm920t'' option when compiling ''fpgaregs'' for APF9328 and ''-mcpu=arm926ej-s'' for APF27.

== PCIe ==

On [[APF6_SP]] FPGA memory is accessed with PCIe, to read/write on FPGA space an example is available with [[Pci_debug | pci_debug]].

=== Pci_debug ===

See [[Pci_debug | pci_debug]] page to know how to access PCIe address space with a command line tool.

==Links==
* http://sources.redhat.com/ml/crossgcc/2005-08/msg00120.html : Explanation of the problem.

Using FPGA

2025-10-09T08:25:23Z

KevinJ: /* FPGA Interfaces */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

==== Accessing the FPGA address domain from Linux userspace ====
* [[FPGA_register | APF9328, APF27, APF51 and OPOS6UL_SP]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
*'''OPOS93_SP'''
** [[OPOS93_SP_FPGA_designing | FPGA designing]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Efinix'''
* [[Efinity]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

Using FPGA

2025-10-09T08:21:09Z

KevinJ: /* FPGA Interfaces */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

==== Accessing the FPGA address domain from Linux ====
* [[FPGA_register | APF9328, APF27, APF51 and OPOS6UL_SP]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
*'''OPOS93_SP'''
** [[OPOS93_SP_FPGA_designing | FPGA designing]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Efinix'''
* [[Efinity]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

OPOS93 SP FPGA configuration

2025-10-03T16:21:42Z

KevinJ: /* Configuration */

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Using Linux ==

=== Prerequisites ===

Please ensure that the [[Efinity]] project is configured as such:
* Generate '''.hex.bin''' file (found under the ''outflow'' directory)
* The bitstream should be in a '''SPI 8b passive''' format

=== Configuration ===

The ''flexio-armabus'' kernel driver will configure the FPGA via SPI as soon as it is loaded.
Please copy your '''<YOUR_PROJECT>.hex.bin''' to ''/lib/firmware/fpga/bitstream.bin'' on the board and either reboot, or unload and reload the module:
<pre class="apf">
# rmmod flexio-armabus
# modprobe flexio-armabus
</pre>

{{Note| On the Opos93SP_Dev board, prior to remove the flexio-armabus, you'll probably need to:
* unbind the '''fpga-gpio-leds''' from the GPIOs:
*:<pre class="apf"> # echo 'fpga-gpio-leds' > /sys/bus/platform/drivers/leds-gpio/unbind</pre>
* Remove the '''gpio_flexio_armabus''' module:
*:<pre class="apf"> # rmmod gpio_flexio_armabus</pre>
}}

== Using Efinity via JTAG ==

{{Warning| Configuring the FPGA using Efinity programmer is currently broken.}}

OPOS93 SP FPGA configuration

2025-10-03T16:11:52Z

KevinJ:

OPOS93 SP FPGA configuration

2025-10-03T16:04:40Z

KevinJ: Created page with "Category: OPOS93_SP Category: FPGA == Using Linux == === Prerequisites == Please ensure that the Efinity project is configured as such: * Generate '''.hex.bin''' file (found under the ''outflow'' directory) * The bitstream should be in a '''SPI 8b passive''' format == Using Efinity via JTAG == {{Warning| Configuring the FPGA using Efinity programmer is currently broken.}}"

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Using Linux ==

=== Prerequisites ==

Please ensure that the [[Efinity]] project is configured as such:
* Generate '''.hex.bin''' file (found under the ''outflow'' directory)
* The bitstream should be in a '''SPI 8b passive''' format

== Using Efinity via JTAG ==

{{Warning| Configuring the FPGA using Efinity programmer is currently broken.}}

OPOS93 SP FPGA designing

2025-10-03T16:00:45Z

KevinJ: /* Requisites */

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Prerequisites ==

You'll need to install [[Efinity]] in order to synthetise your design for the embedded Efinix Trion T20.

== Starting from a template project ==

Template projects for [[Chisel | Chisel]] or Verilog/VHDL development are publicly available on the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository].

== Chisel ==

# Install [https://www.scala-sbt.org/download/ Scala/SBT] on your environment
# Setup a Chisel project and add the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper] as a dependency
# From the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository], copy the ''opos93sp-template'' or ''opos93sp-template-wb'' (with Wishbone bus instantiated) folder from the ''hardware'' directory.
# You can then hack the different files:
#*'''Makefile''': change your project name, change your Chisel project's directory, ...
#*'''generate-project.py''': IO configurations of the FPGA (see documentation from Efinix)
# Load [[Efinity]]'s environment variables (do it only one time):
#:<pre class="host">$ source <EFINITY_PATH>/bin/setup.sh</pre>
# Build the project
#: <pre class="host"> $ make </pre>

== Verilog/VHDL ==

The [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository] build template projects for every releases. Those tamplate projects can be found under the asset section on [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper/-/releases the release page].

# Download the '''Opos93SP template project''' or the '''Opos93SP wishbone template project''' whether you need a Wishbone bus or not.
# Open the project in [[Efinity]] and start hacking the generated wishbone or FlexIO Verilog modules depending on the template project you chose in the step above.

= JTAG Debugging =

JTAG debugging using [[Efinity]] can be achieved following this procedure:
# Synthetise the design (only the ''Synthetise'' step is required)
# Generate a debug core using the "Debug Wizard" of Efinity
# Add the signals you are interested in
# Generate the bitstream (you can skip the ''Synthesis' step and resume from the ''Mapping'' step)
# [[OPOS93_SP_FPGA_configuration | Configure the FPGA]] with the generated bitstream
# Open the Efinity debugger and attach the target

Now you should be able to trigger acquisition, see instant signal values, etc ...

OPOS93 SP FPGA designing

2025-10-03T15:54:03Z

KevinJ:

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Requisites ==

You'll need to install [[Efinity]] in order to synthetise your design for the embedded Efinix Trion T20.

== Starting from a template project ==

Template projects for [[Chisel | Chisel]] or Verilog/VHDL development are publicly available on the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository].

== Chisel ==

# Install [https://www.scala-sbt.org/download/ Scala/SBT] on your environment
# Setup a Chisel project and add the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper] as a dependency
# From the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository], copy the ''opos93sp-template'' or ''opos93sp-template-wb'' (with Wishbone bus instantiated) folder from the ''hardware'' directory.
# You can then hack the different files:
#*'''Makefile''': change your project name, change your Chisel project's directory, ...
#*'''generate-project.py''': IO configurations of the FPGA (see documentation from Efinix)
# Load [[Efinity]]'s environment variables (do it only one time):
#:<pre class="host">$ source <EFINITY_PATH>/bin/setup.sh</pre>
# Build the project
#: <pre class="host"> $ make </pre>

== Verilog/VHDL ==

The [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository] build template projects for every releases. Those tamplate projects can be found under the asset section on [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper/-/releases the release page].

# Download the '''Opos93SP template project''' or the '''Opos93SP wishbone template project''' whether you need a Wishbone bus or not.
# Open the project in [[Efinity]] and start hacking the generated wishbone or FlexIO Verilog modules depending on the template project you chose in the step above.

= JTAG Debugging =

JTAG debugging using [[Efinity]] can be achieved following this procedure:
# Synthetise the design (only the ''Synthetise'' step is required)
# Generate a debug core using the "Debug Wizard" of Efinity
# Add the signals you are interested in
# Generate the bitstream (you can skip the ''Synthesis' step and resume from the ''Mapping'' step)
# [[OPOS93_SP_FPGA_configuration | Configure the FPGA]] with the generated bitstream
# Open the Efinity debugger and attach the target

Now you should be able to trigger acquisition, see instant signal values, etc ...

OPOS93 SP FPGA designing

2025-10-03T15:26:19Z

KevinJ: /* Chisel */

Efinity

2025-10-03T15:25:09Z

KevinJ: /* Linux */

[[Category: FPGA]]
[[Category: Efinix]]

[https://www.efinixinc.com/products-efinity.html Product page]

== Install ==

=== Linux ===

Please follow the install instruction from the manufacturer. Don't forget to apply the patch!

Then, before using the tool, you need to load the environment variables:
<pre class="host">$ source <EFINITY_PATH>/bin/setup.sh</pre>

== Add Trenz TEI0004 JTAG adapter profile ==

Create the '''<EFINITY_PATH>/pgm/bin/efx_pgm/efx_hw_common/boards/trenz_tei0004.json''' file with the following:

<source lang="json">
{
"name": "Arrow USB Blaster TEI0004",
"programmer": {
"programmer_type": "ftdi_program",
"supported_mode": ["JTAG"]
},
"usb": {
"vid": "0x0403",
"pid": "0x6010",
"desc": "Arrow USB Blaster TEI0004"
},
"pinout": {
"CBUS0": "",
"CBUS1": "",
"CBUS2": "",
"CCK": "",
"CDI0": "",
"CDI1": "",
"CDI2": "",
"CDI3": "",
"SS": "",
"CRESET_N": "",
"CONDONE": "",
"HOLD": "",
"TCK": "FTDI_ADBUS0",
"TDI": "FTDI_ADBUS1",
"TDO": "FTDI_ADBUS2",
"TMS": "FTDI_ADBUS3"
},
"init": {
"val": "",
"dir": ""
}
}
</source>

Efinity

2025-10-03T15:24:54Z

KevinJ: /* Linux */

[[Category: FPGA]]
[[Category: Efinix]]

[https://www.efinixinc.com/products-efinity.html Product page]

== Install ==

=== Linux ===

Please follow the install instruction from the manufacturer. Don't forget to apply the patch!

Then, before using the tool, you need to load the environment variables:
<pre class="host">source <EFINITY_PATH>/bin/setup.sh</pre>

== Add Trenz TEI0004 JTAG adapter profile ==

Create the '''<EFINITY_PATH>/pgm/bin/efx_pgm/efx_hw_common/boards/trenz_tei0004.json''' file with the following:

<source lang="json">
{
"name": "Arrow USB Blaster TEI0004",
"programmer": {
"programmer_type": "ftdi_program",
"supported_mode": ["JTAG"]
},
"usb": {
"vid": "0x0403",
"pid": "0x6010",
"desc": "Arrow USB Blaster TEI0004"
},
"pinout": {
"CBUS0": "",
"CBUS1": "",
"CBUS2": "",
"CCK": "",
"CDI0": "",
"CDI1": "",
"CDI2": "",
"CDI3": "",
"SS": "",
"CRESET_N": "",
"CONDONE": "",
"HOLD": "",
"TCK": "FTDI_ADBUS0",
"TDI": "FTDI_ADBUS1",
"TDO": "FTDI_ADBUS2",
"TMS": "FTDI_ADBUS3"
},
"init": {
"val": "",
"dir": ""
}
}
</source>

Efinity

2025-10-03T15:24:25Z

KevinJ: /* Install */

[[Category: FPGA]]
[[Category: Efinix]]

[https://www.efinixinc.com/products-efinity.html Product page]

== Install ==

=== Linux ===

Please follow the install instruction from the manufacturer. Don't forget to apply the patch!

Then, before using the tool, you need to load the environment variables:
source <EFINITY_PATH>/bin/setup.sh

== Add Trenz TEI0004 JTAG adapter profile ==

Create the '''<EFINITY_PATH>/pgm/bin/efx_pgm/efx_hw_common/boards/trenz_tei0004.json''' file with the following:

<source lang="json">
{
"name": "Arrow USB Blaster TEI0004",
"programmer": {
"programmer_type": "ftdi_program",
"supported_mode": ["JTAG"]
},
"usb": {
"vid": "0x0403",
"pid": "0x6010",
"desc": "Arrow USB Blaster TEI0004"
},
"pinout": {
"CBUS0": "",
"CBUS1": "",
"CBUS2": "",
"CCK": "",
"CDI0": "",
"CDI1": "",
"CDI2": "",
"CDI3": "",
"SS": "",
"CRESET_N": "",
"CONDONE": "",
"HOLD": "",
"TCK": "FTDI_ADBUS0",
"TDI": "FTDI_ADBUS1",
"TDO": "FTDI_ADBUS2",
"TMS": "FTDI_ADBUS3"
},
"init": {
"val": "",
"dir": ""
}
}
</source>

OPOS93 SP FPGA designing

2025-10-03T15:23:33Z

KevinJ: /* Chisel */

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Requisites ==

You'll need to install [[Efinity]] in order to synthetise your design for the embedded Efinix Trion T20.

== Starting from a template project ==

Template projects for [[Chisel | Chisel]] or Verilog/VHDL development are publicly available on the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository].

== Chisel ==

# Install [https://www.scala-sbt.org/download/ Scala/SBT] on your environment
# Setup a Chisel project and add the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper] as a dependency
# From the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository], copy the ''opos93sp-template'' or ''opos93sp-template-wb'' (with Wishbone bus instantiated) folder from the ''hardware'' directory.
# You can then hack the different files:
#*'''Makefile''': change your project name, change your Chisel project's directory, ...
#*'''generate-project.py''': IO configurations of the FPGA (see documentation from Efinix)
# Build the project
#: <pre class="host"> $ make </pre>

== Verilog/VHDL ==

The [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository] build template projects for every releases. Those tamplate projects can be found under the asset section on [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper/-/releases the release page].

# Download the '''Opos93SP template project''' or the '''Opos93SP wishbone template project''' whether you need a Wishbone bus or not.
# Open the project in [[Efinity]] and start hacking the generated wishbone or FlexIO Verilog modules depending on the template project you chose in the step above.

Efinity

2025-10-03T15:21:25Z

KevinJ:

[[Category: FPGA]]
[[Category: Efinix]]

[https://www.efinixinc.com/products-efinity.html Product page]

== Install ==

=== Linux ===

Please follow the install instruction from the manufacturer. Don't forget to apply the patch!

== Add Trenz TEI0004 JTAG adapter profile ==

Create the '''<EFINITY_PATH>/pgm/bin/efx_pgm/efx_hw_common/boards/trenz_tei0004.json''' file with the following:

<source lang="json">
{
"name": "Arrow USB Blaster TEI0004",
"programmer": {
"programmer_type": "ftdi_program",
"supported_mode": ["JTAG"]
},
"usb": {
"vid": "0x0403",
"pid": "0x6010",
"desc": "Arrow USB Blaster TEI0004"
},
"pinout": {
"CBUS0": "",
"CBUS1": "",
"CBUS2": "",
"CCK": "",
"CDI0": "",
"CDI1": "",
"CDI2": "",
"CDI3": "",
"SS": "",
"CRESET_N": "",
"CONDONE": "",
"HOLD": "",
"TCK": "FTDI_ADBUS0",
"TDI": "FTDI_ADBUS1",
"TDO": "FTDI_ADBUS2",
"TMS": "FTDI_ADBUS3"
},
"init": {
"val": "",
"dir": ""
}
}
</source>

Efinity

2025-10-03T15:16:21Z

KevinJ: Created page with "Category: FPGA Category: Efinix https://www.efinixinc.com/products-efinity.html Product page"

[[Category: FPGA]]
[[Category: Efinix]]

[[https://www.efinixinc.com/products-efinity.html Product page]]

OPOS93 SP FPGA designing

2025-10-03T15:13:46Z

KevinJ: Created page with "Category: OPOS93_SP Category: FPGA == Requisites == You'll need to install Efinity in order to synthetise your design for the embedded Efinix Trion T20. == Starting from a template project == Template projects for Chisel or Verilog/VHDL development are publicly available on the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository]. == Chisel == # Install [https://www.scala-sb..."

[[Category: OPOS93_SP]]
[[Category: FPGA]]

== Requisites ==

You'll need to install [[Efinity]] in order to synthetise your design for the embedded Efinix Trion T20.

== Starting from a template project ==

Template projects for [[Chisel | Chisel]] or Verilog/VHDL development are publicly available on the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository].

== Chisel ==

# Install [https://www.scala-sbt.org/download/ Scala/SBT] on your environment
# Setup a Chisel project and add the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper] as a dependency
# From the [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository], copy the ''opos93sp-template'' or ''opos93sp-template-wb'' (with Wishbone bus instantiated) folder from the ''hardware'' directory.
# You can then hack the different files:
#*'''Makefile''': change your project name, change your Chisel project's directory, ...
#*'''generate-project.py''': IO configurations of the FPGA (see documentation from [[Efinity]])
# Build the project
#: <pre class="host"> $ make </pre>

== Verilog/VHDL ==

The [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper flexIO to Wishbone bus wrapper repository] build template projects for every releases. Those tamplate projects can be found under the asset section on [https://git.armadeus.com/armadeus/armadeus-gateware/flexio-wishbone-wrapper/-/releases the release page].

# Download the '''Opos93SP template project''' or the '''Opos93SP wishbone template project''' whether you need a Wishbone bus or not.
# Open the project in [[Efinity]] and start hacking the generated wishbone or FlexIO Verilog modules depending on the template project you chose in the step above.

Using FPGA

2025-10-03T14:59:59Z

KevinJ: /* Design Tools */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

* [[FPGA_register | Access the FPGA address domain from Linux]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
*'''OPOS93_SP'''
** [[OPOS93_SP_FPGA_designing | FPGA designing]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Efinix'''
* [[Efinity]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

Using FPGA

2025-10-03T14:05:31Z

KevinJ: /* FPGA designing on Armadeus platforms */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

* [[FPGA_register | Access the FPGA address domain from Linux]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
*'''OPOS93_SP'''
** [[OPOS93_SP_FPGA_designing | FPGA designing]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

Using FPGA

2025-10-03T14:03:49Z

KevinJ: /* Configuring Armadeus platform's FPGA */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

* [[FPGA_register | Access the FPGA address domain from Linux]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

Uboot FPGA firmware update from Linux

2025-10-03T14:03:31Z

KevinJ: Blanked the page

APF9328 APF27 APF51 OPOS6UL SP FPGA configuration

2025-10-03T14:03:08Z

KevinJ: /* Configuring from Linux */

[[Category: APF9328]]
[[Category: APF27]]
[[Category: APF51]]
[[Category: OPOS6UL_SP]]
[[Category: FPGA]]

== Test bitstream ==

* The FPGA bitstreams are all located in the ''firmware/'' directory of your Armadeus BSP sources:
<pre class="host">
$ ls firmware/
apf_pkg BRAMTest bus_led led PS2 PS2_Opencore servo sram_test wishbone_example Xtools
</pre>
* You can make some trials with the ''firmware/leds/blinking_led/bin/'' files.
<br>

== Configuring from Linux ==

=== Directly ===

Please use the [[FPGA_loader | FPGA loader linux driver]].

{{Warning | For APF51, please use binary format '''.bin''', bitstream format '''.bit''' doesn't work.}}

=== Flashing the FPGA firmware partition ===

The FPGA firmware partition (mainly used from U-Boot) can be updated by means of U-Boot (see [[APF9328_APF27_APF51_OPOS6UL_SP_FPGA_configuration#Configuring_from_uBoot|here]]) or directly from Linux as described herewith.

Under Linux:

* At first, download your FPGA firmware:
<pre class="apf">
# tftp -g -r my_firmware.bit 192.168.0.2
</pre>

* Then, determine which partition in the flash is the firmware partition:
<pre class="apf">
# cat /proc/mtd
dev: size erasesize name
mtd0: 00100000 00020000 "u-boot"
mtd1: 00080000 00020000 "env"
mtd2: 00080000 00020000 "env2"
mtd3: 00100000 00020000 "firmware"
mtd4: 00080000 00020000 "dtb"
mtd5: 00080000 00020000 "splash"
mtd6: 00800000 00020000 "kernel"
mtd7: 1f400000 00020000 "rootfs"
</pre>
The example above is taken from an APF51 running Armadeus version 5.2 and we can see that mtd3 is the firmware partition. If yours is different, then replace mtd3 by what you found out to be the right one in the following commands.

* Once done, the firmware partition has to be erased:
<pre class="apf">
# flash_erase /dev/mtd3 0 0
</pre>

* Then your FPGA .bit file can be written:
<pre class="apf">
# nandwrite -p /dev/mtd3 my_firmware.bit
</pre>

== Configuring from uBoot ==

{{Warning| for the APF9328, please check that your bitfile size is smaller than the firmware partition size (256KB) before trying the following commands or you may corrupt your Linux kernel FLASH partition !!!}}

{{Note | For the APF51 and U-Boot versions earlier than 2013.04, only binary file format ('''.bin''') can be used; do not try '''.bit''' file. <br> For the APF51 and U-Boot versions 2013.04 or later you can also use .bit files with the U-Boot command: <pre class="apf"> BIOS> fpga loadb </pre>}}

* '''Step 1''': instal/copy your firmware to /tftpboot
** manually: <pre class="host"> $ cp myfirmware.bin /tftpboot/apfXX-firmware.bin (where apfXX is the name of your board: apf27, apf51 or apf9328)</pre>
** using the armadeus BSP: <pre class="host"> $ make menuconfig</pre>
*:<pre class="config">Package Selection for the target ---> Armadeus specific tools/utilities ---></pre>
** specify the path to the FPGA firmware:
<pre line class="config">
[*] FPGA Firmware
Firmware to install (Install a custom FPGA firmware) --->
($(TOPDIR)/../firmware/leds/blinking_led/bin/blinking_led_apf27_200k.bit) FPGA binary file path
[*] Export this file to Buildroot images folder
</pre>
**<pre class="host"> $ cp buildroot/output/images/* /tftpboot </pre>

* '''Step 2''': Load FPGA firmware image file with U-Boot through Ethernet:
<pre class="apf">
BIOS> tftpboot ${loadaddr} fpgafirmware.bin
</pre>
''fpgafirmware.bin'' is of course the name of your bitfile stored in your TFTP shared directory (''/tftpboot/'')

then you can type the c command to reconnect to the terminal

* '''Step 3''': Test your new FPGA firmware's downloading:
** for .bin binary files <pre class="apf">BIOS> fpga load 0 ${loadaddr} ${filesize}</pre>
** for .bit binary files <pre class="apf">BIOS> fpga loadb 0 ${loadaddr} ${filesize}</pre>

=== Using U-Boot scripts ===

For your convenience a set of U-Boot script to facilitate firmware management with the APF boards:
* ''download_firmware'': assuming your firmware is in /tftpboot and name apfXX-firmware.bin (where apfXX is the name of your board apf27, apf51, apf9328..) will download the firmware in RAM with the command: run download_firmware
* ''flash_firmware'': save the previously downloaded firmware from RAM into the flash.
* ''update_firmware'': will execute the previous 2 scripts in sequence.
* ''load_firmware'': read a firmware from the flash (there is dedication partition named firmware for this purpose) and load it into the FPGA.

Download and test your firmware image with:
<pre class="apf">
BIOS> run download_firmware
BIOS> run load_firmware
</pre>

=== Autoloading ===
When you are satisfied with your firmware, you can write it in flash make it "autoloaded" at power up:
{{Warning| '''Before''' setting the firmware_autoload variable, be sure that your FPGA binary file is correct. If not, your board will '''hang up''' at U-Boot start and you will need to cancel the fpga download to take control of the board. see note below}}
<pre class="apf">
BIOS> run update_firmware
BIOS> setenv firmware_autoload 1
BIOS> saveenv
</pre>

{{Note | (U-Boot 2012.04) you can manually cancel the firmware autoload using the following procedure: keeping <CTRL-C> pressed on the console and power up the board will start the board without downloading the FPGA firmware - This procedure can be helpfull if you have programmed a broken firmware }}

Using FPGA

2025-10-03T13:57:54Z

KevinJ: /* FPGA Interfaces */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

* [[FPGA_register | Access the FPGA address domain from Linux]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

* Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}