ArmadeusWiki - User contributions [en]

OPOSA5E SP Interface description

2026-10-30T09:10:44Z

FabienM: /* Interfaces */

[[Category: OPOSA5E_SP]]
[[Category: Agilex5]]
[[Category: FPGA]]

== Introduction ==

The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone.

[[File:oposa5e_sp_agilex5_bridges.jpg|Bridges HPS-FPGA|center]]

== Interfaces ==

There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5

* FPGA-to-HPS (F2H) : 256b ACE5-Lite
* HPS-to-FPGA (H2F) : 32/64/128 bits AXI4 interface
* Lightweight HPS-to-FPGA (LWH2F) : 32 bits AXI4 interface
* FPGA-to-SDRAM (F2SDRAM) : 256b/128b/64b AXI-4

The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website]

2 bridges can be directly used from HPS to read/write access :

{| class="wikitable" style="margin:auto"
|+ Bridge address
|-
! Bridge !! Offset !! size
|-
| HPS-to-FPGA (H2F) || 00_4000_0000 || 1 GB
|-
| Lightweight HPS-to-FPGA (LWH2F) || 00_2000_0000 ||512 MB
|}

Bridge must be activated before use with `bridge` command in [https://u-boot-project.org/ U-Boot] :
<pre class="apf">
OPOSA5E_SP # bridge -h
bridge - SoCFPGA HPS FPGA bridge control

Usage:
bridge enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10
For example:
1) To enable and disable all bridges (command without mask):
a) bridge enable
b) bridge disable
2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask):
a) bridge enable 0x3
b) bridge disable 0x3
</pre>

For example, to activate the LWH2F bridge do :

<pre class="apf">
OPOSA5E_SP # bridge enable 0x2
</pre>

Accesses can be done in U-Boot with `md.l` and `mw.l` commands:

<pre class="apf">
OPOSA5E_SP # md.l 0x20010060 1
20010060: 0000000e ....
</pre>

[[Using_FPGA| << FPGA general page]]

OPOSA5E SP Interface description

2026-10-30T09:07:30Z

FabienM: /* Interfaces */

[[Category: OPOSA5E_SP]]
[[Category: Agilex5]]
[[Category: FPGA]]

== Introduction ==

The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone.

[[File:oposa5e_sp_agilex5_bridges.jpg|Bridges HPS-FPGA|center]]

== Interfaces ==

There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5

* FPGA-to-HPS (F2H) : 256b ACE5-Lite
* HPS-to-FPGA (H2F) : 32/64/128 bits AXI4 interface
* Lightweight HPS-to-FPGA (LWH2F) : 32 bits AXI4 interface
* FPGA-to-SDRAM (F2SDRAM) : 256b/128b/64b AXI-4

The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website]

2 bridges can be directly used from HPS to read/write access :

{| class="wikitable" style="margin:auto"
|+ Bridge address
|-
! Bridge !! Offset !! size
|-
| HPS-to-FPGA (H2F) || 00_4000_0000 || 1 GB
|-
| Lightweight HPS-to-FPGA (LWH2F) || 00_2000_0000 ||512 MB
|}

Bridge must be activated before use with `bridge` command in uboot :
<pre class="apf">
OPOSA5E_SP # bridge -h
bridge - SoCFPGA HPS FPGA bridge control

Usage:
bridge enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10
For example:
1) To enable and disable all bridges (command without mask):
a) bridge enable
b) bridge disable
2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask):
a) bridge enable 0x3
b) bridge disable 0x3
</pre>

For example, to activate the LWH2F bridge do :

<pre class="apf">
OPOSA5E_SP # bridge enable 0x2
</pre>

[[Using_FPGA| << FPGA general page]]

OPOSA5E SP Interface description

2026-10-30T09:07:04Z

FabienM: /* Interfaces */

[[Category: OPOSA5E_SP]]
[[Category: Agilex5]]
[[Category: FPGA]]

== Introduction ==

The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone.

[[File:oposa5e_sp_agilex5_bridges.jpg|Bridges HPS-FPGA|center]]

== Interfaces ==

There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5

* FPGA-to-HPS (F2H) : 256b ACE5-Lite
* HPS-to-FPGA (H2F) : 32/64/128 bits AXI4 interface
* Lightweight HPS-to-FPGA (LWH2F) : 32 bits AXI4 interface
* FPGA-to-SDRAM (F2SDRAM) : 256b/128b/64b AXI-4

The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website]

2 bridges can be directly used from HPS to read/write access :

{| class="wikitable" style="margin:auto"
|+ Bridge address
|-
! Bridge !! Offset !! size
|-
| HPS-to-FPGA (H2F) || 00_4000_0000 || 1 GB
|-
| Lightweight HPS-to-FPGA (LWH2F) || 00_2000_0000 ||512 MB
|}

Bridge must be activated before use :

* With `bridge` command in uboot :
<pre class="apf">
OPOSA5E_SP # bridge -h
bridge - SoCFPGA HPS FPGA bridge control

Usage:
bridge enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10
For example:
1) To enable and disable all bridges (command without mask):
a) bridge enable
b) bridge disable
2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask):
a) bridge enable 0x3
b) bridge disable 0x3
</pre>

For example, to activate the LWH2F bridge do :

<pre class="apf">
OPOSA5E_SP # bridge enable 0x2
</pre>

[[Using_FPGA| << FPGA general page]]

OPOSA5E SP Interface description

2026-10-30T08:59:46Z

FabienM: /* Interfaces */

[[Category: OPOSA5E_SP]]
[[Category: Agilex5]]
[[Category: FPGA]]

== Introduction ==

The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone.

[[File:oposa5e_sp_agilex5_bridges.jpg|Bridges HPS-FPGA|center]]

== Interfaces ==

There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5

* FPGA-to-HPS (F2H) : 256b ACE5-Lite
* HPS-to-FPGA (H2F) : 32/64/128 bits AXI4 interface
* Lightweight HPS-to-FPGA (LWH2F) : 32 bits AXI4 interface
* FPGA-to-SDRAM (F2SDRAM) : 256b/128b/64b AXI-4

The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website]

2 bridges can be directly used from HPS to read/write access :

* HPS-to-FPGA (H2F) : 32/64/128 bits AXI4 interface
* Lightweight HPS-to-FPGA (LWH2F) : 32 bits AXI4 interface

Bridge must be activated before use :

* With `bridge` command in uboot :
<pre class="apf">
OPOSA5E_SP # bridge -h
bridge - SoCFPGA HPS FPGA bridge control

Usage:
bridge enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10
For example:
1) To enable and disable all bridges (command without mask):
a) bridge enable
b) bridge disable
2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask):
a) bridge enable 0x3
b) bridge disable 0x3
</pre>

For example, to activate the LWH2F bridge do :

<pre class="apf">
OPOSA5E_SP # bridge enable 0x2
</pre>

[[Using_FPGA| << FPGA general page]]

OPOSA5E SP Interface description

2026-10-30T08:52:07Z

FabienM: /* Introduction */

[[Category: OPOSA5E_SP]]
[[Category: Agilex5]]
[[Category: FPGA]]

== Introduction ==

The Agilex5 is a FPGA mounted on Oposa5e_sp. This SoC is composed of hps processor core and FPGA logic zone.

[[File:oposa5e_sp_agilex5_bridges.jpg|Bridges HPS-FPGA|center]]

== Interfaces ==

There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5

* FPGA-to-HPS (F2H) bridge
* HPS-to-FPGA (H2F) bridge
* Lightweight HPS-to-FPGA (LWH2F) bridge
* FPGA-to-SDRAM (F2SDRAM) bridge

The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website]

Bridge must be activated before use :

* With `bridge` command in uboot :
<pre class="apf">
OPOSA5E_SP # bridge -h
bridge - SoCFPGA HPS FPGA bridge control

Usage:
bridge enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2), F2SDRAM0 (Bit 3), F2SDRAM1 (Bit 4), F2SDRAM2 (Bit 5) bridges
Bit 3, Bit 4 and Bit 5 bridges only available in Stratix 10
For example:
1) To enable and disable all bridges (command without mask):
a) bridge enable
b) bridge disable
2) To enable and disable HPS-to-FPGA and LWHPS-to-FPGA bridges (command with mask):
a) bridge enable 0x3
b) bridge disable 0x3
</pre>

For example, to activate the LWH2F bridge do :

<pre class="apf">
OPOSA5E_SP # bridge enable 0x2
</pre>

[[Using_FPGA| << FPGA general page]]

File:Oposa5e sp agilex5 bridges.jpg

2026-10-30T08:28:44Z

FabienM: FabienM uploaded a new version of File:Oposa5e sp agilex5 bridges.jpg

File:Oposa5e sp agilex5 bridges.jpg

2026-10-30T08:26:14Z

FabienM: FabienM uploaded a new version of File:Oposa5e sp agilex5 bridges.jpg

File:Oposa5e sp agilex5 bridges.jpg

2026-10-30T08:23:38Z

FabienM:

OPOSA5E SP Interface description

2026-10-30T08:23:23Z

FabienM: /* Introduction */

[[Category: OPOSA5E_SP]]
[[Category: Agilex5]]
[[Category: FPGA]]

== Introduction ==

[[File:oposa5e_sp_agilex5_bridges.jpg|caption]]

There are 4 bridges connecting the HPS to the FPGA portion of the Agilex5

* FPGA-to-HPS (F2H) bridge
* HPS-to-FPGA (H2F) bridge
* Lightweight HPS-to-FPGA (LWH2F) bridge
* FPGA-to-SDRAM (F2SDRAM) bridge

The full documentation is available on [https://docs.altera.com/r/docs/814346/26.1.1/hard-processor-system-technical-reference-manual-agilex-5-socs/bridges Altera website]

[[Using_FPGA| << FPGA general page]]

FPGA registers access from Linux userspace on APF9328, APF27 SP, APF51 SP and OPOS6UL SP

2026-10-22T09:11:11Z

FabienM: /* Introduction */

[[Category:FPGA]]
[[Category: APF9328]]
[[Category: APF27]]
[[Category: APF51]]
[[Category: OPOS6UL_SP]]

== Introduction ==

For '''APF9328, APF27, APF51 and OPOS6UL_SP''', registers access are done with a memory bus (parallel).
Access through this bus can be made by two methods:
* Using ''fpgaregs'' tool

{{Warning| With defaults wishbone wrappers, FPGA are configured for '''16 bits accesses''' for [[APF9328]], [[APF27]], [[APF51]] and [[OPOS6UL_SP]]. To make 32 bits access, (W)EIM bus configuration and HDL wrapper must be modified.}}

== fpgaregs ==
===Installation===
If the fpgaregs package is not already installed on your APF (''/usr/bin/fpgaregs''), you can select it in the Buildroot menuconfig:
<pre class="host">
$ make menuconfig
</pre>

<pre class="config">
Package Selection for the target --->
[*] Hardware handling / blockdevices and filesystem maintenance --->
[*] fpgaregs
</pre>

<pre class="host">
$ make
</pre>

Then reflash your rootfs or install it manually.

===Usage===

''fpgaregs'' can be used to do read or write accesses (16 or 32 bits wide) to the FPGA, from Linux userspace/console.

====16 bits read====
<pre class="apf">
# fpgaregs w <address>
</pre>

Where <address> is an address relative to FPGA's mapping in hexadecimal value. Example:
<pre class="apf">
# fpgaregs w 0
</pre>

====16 bits write====
<pre class="apf">
# fpgaregs w <address> <value>
</pre>

Where <value> is hexadecimal value to write.

====32 bits read====
<pre class="apf">
# fpgaregs l <address>
</pre>

====32 bits write====
<pre class="apf">
# fpgaregs l <address> <value>
</pre>

== the mmap problem ==

{{Note| This problem is corrected with latest Toolchains compilation options}}

First of all, you need to get a file descriptor for ''/dev/mem'' using the ''open()'' function
<source lang="c">
ffpga=open("/dev/mem",O_RDWR|O_SYNC);
</source>
Now you have a valid file descriptor to access your FPGA.

The O_SYNC option is recommended to avoid Linux to cache the content of /dev/mem and delay any modification done in this file.

To access fpga register, fpgaregs use the ''mmap()'' system call :

<source lang="c">
void * ptr_fpga;
ptr_fpga = mmap (0, 8192, PROT_READ|PROT_WRITE, MAP_SHARED, ffpga, FPGA_ADDRESS);
</source>

Thanks to this function, fpga registers are accessible directly on memory with pointer ptr_fpga. To read and write in 16bits or in 32 bits we will cast the pointer value in ''unsigned short'' or ''unsigned int'' :

'''16bits'''
''write''
<source lang="c">
*(unsigned short*)(ptr_fpga+(address)) = (unsigned short)value;
</source>
''read''
<source lang="c">
value = *(unsigned short*)(ptr_fpga+(address));
</source>

'''32 bits'''
''write''
<source lang="c">
*(unsigned int*)(ptr_fpga+(address)) = (unsigned short)value;
</source>

''read''
<source lang="c">
value = *(unsigned int*)(ptr_fpga+(address));
</source>

=== The problem ===

By default, if the specific ''arm920t'' target is not specified, ''arm-linux-gcc'' will try to generate compatible read/write for all ARM9 model when it access register in 16bits. Indeed it seems that not all ARM9 have 16bits read/write capabilities (''ldrh'' asm instruction).

As the interface between i.MXL and FPGA on APF9328 has no 8bits read/write capabilities, each 8 bits access is recognized by the FPGA as a 16bits access. So on each 16bits access of the i.MXL, FPGA will process two 16bits access instead of 1. That is a problem when accessing a FIFO for example.

To avoid this painful problem don't forget the ''-mcpu=arm920t'' option when compiling ''fpgaregs'' for APF9328 and ''-mcpu=arm926ej-s'' for APF27.

==Links==
* http://sources.redhat.com/ml/crossgcc/2005-08/msg00120.html : Explanation of the problem.

FPGA registers access from Linux userspace on APF9328, APF27 SP, APF51 SP and OPOS6UL SP

2026-10-22T09:10:47Z

FabienM: /* Introduction */

[[Category:FPGA]]
[[Category: APF9328]]
[[Category: APF27]]
[[Category: APF51]]
[[Category: OPOS6UL_SP]]

== Introduction ==

For '''APF9328, APF27, APF51 and OPOS6UL_SP''', registers access are done with a memory bus (parallel).
Access through this bus can be made by two methods:
* Using ''fpgaregs'' tool

{{Warning| With defaults wishbone wrappers, FPGA are configured for '''16 bits accesses''' for [[APF9328]], [[APF27]], [[APF51]] and [[OPOS6UL_SP]]. To make 32bits access, (W)EIM bus configuration and HDL wrappers must be modified.}}

== fpgaregs ==
===Installation===
If the fpgaregs package is not already installed on your APF (''/usr/bin/fpgaregs''), you can select it in the Buildroot menuconfig:
<pre class="host">
$ make menuconfig
</pre>

<pre class="config">
Package Selection for the target --->
[*] Hardware handling / blockdevices and filesystem maintenance --->
[*] fpgaregs
</pre>

<pre class="host">
$ make
</pre>

Then reflash your rootfs or install it manually.

===Usage===

''fpgaregs'' can be used to do read or write accesses (16 or 32 bits wide) to the FPGA, from Linux userspace/console.

====16 bits read====
<pre class="apf">
# fpgaregs w <address>
</pre>

Where <address> is an address relative to FPGA's mapping in hexadecimal value. Example:
<pre class="apf">
# fpgaregs w 0
</pre>

====16 bits write====
<pre class="apf">
# fpgaregs w <address> <value>
</pre>

Where <value> is hexadecimal value to write.

====32 bits read====
<pre class="apf">
# fpgaregs l <address>
</pre>

====32 bits write====
<pre class="apf">
# fpgaregs l <address> <value>
</pre>

== the mmap problem ==

{{Note| This problem is corrected with latest Toolchains compilation options}}

First of all, you need to get a file descriptor for ''/dev/mem'' using the ''open()'' function
<source lang="c">
ffpga=open("/dev/mem",O_RDWR|O_SYNC);
</source>
Now you have a valid file descriptor to access your FPGA.

The O_SYNC option is recommended to avoid Linux to cache the content of /dev/mem and delay any modification done in this file.

To access fpga register, fpgaregs use the ''mmap()'' system call :

<source lang="c">
void * ptr_fpga;
ptr_fpga = mmap (0, 8192, PROT_READ|PROT_WRITE, MAP_SHARED, ffpga, FPGA_ADDRESS);
</source>

Thanks to this function, fpga registers are accessible directly on memory with pointer ptr_fpga. To read and write in 16bits or in 32 bits we will cast the pointer value in ''unsigned short'' or ''unsigned int'' :

'''16bits'''
''write''
<source lang="c">
*(unsigned short*)(ptr_fpga+(address)) = (unsigned short)value;
</source>
''read''
<source lang="c">
value = *(unsigned short*)(ptr_fpga+(address));
</source>

'''32 bits'''
''write''
<source lang="c">
*(unsigned int*)(ptr_fpga+(address)) = (unsigned short)value;
</source>

''read''
<source lang="c">
value = *(unsigned int*)(ptr_fpga+(address));
</source>

=== The problem ===

By default, if the specific ''arm920t'' target is not specified, ''arm-linux-gcc'' will try to generate compatible read/write for all ARM9 model when it access register in 16bits. Indeed it seems that not all ARM9 have 16bits read/write capabilities (''ldrh'' asm instruction).

As the interface between i.MXL and FPGA on APF9328 has no 8bits read/write capabilities, each 8 bits access is recognized by the FPGA as a 16bits access. So on each 16bits access of the i.MXL, FPGA will process two 16bits access instead of 1. That is a problem when accessing a FIFO for example.

To avoid this painful problem don't forget the ''-mcpu=arm920t'' option when compiling ''fpgaregs'' for APF9328 and ''-mcpu=arm926ej-s'' for APF27.

==Links==
* http://sources.redhat.com/ml/crossgcc/2005-08/msg00120.html : Explanation of the problem.

FPGA registers access from Linux userspace on APF9328, APF27 SP, APF51 SP and OPOS6UL SP

2026-10-22T09:10:13Z

FabienM: /* Introduction */

[[Category:FPGA]]
[[Category: APF9328]]
[[Category: APF27]]
[[Category: APF51]]
[[Category: OPOS6UL_SP]]

== Introduction ==

For '''APF9328, APF27, APF51 and OPOS6UL_SP''', registers access are done with a memory bus (parallel).
Access through this bus can be made by two methods:
* Using ''fpgaregs'' tool

{{Warning| With defaults wishbone wrappers FPGA accesses are configured in '''16 bits accesses''' for [[APF9328]], [[APF27]], [[APF51]] and [[OPOS6UL_SP]]. To make 32bits access, (W)EIM bus configuration and HDL wrappers must be modified.}}

== fpgaregs ==
===Installation===
If the fpgaregs package is not already installed on your APF (''/usr/bin/fpgaregs''), you can select it in the Buildroot menuconfig:
<pre class="host">
$ make menuconfig
</pre>

<pre class="config">
Package Selection for the target --->
[*] Hardware handling / blockdevices and filesystem maintenance --->
[*] fpgaregs
</pre>

<pre class="host">
$ make
</pre>

Then reflash your rootfs or install it manually.

===Usage===

''fpgaregs'' can be used to do read or write accesses (16 or 32 bits wide) to the FPGA, from Linux userspace/console.

====16 bits read====
<pre class="apf">
# fpgaregs w <address>
</pre>

Where <address> is an address relative to FPGA's mapping in hexadecimal value. Example:
<pre class="apf">
# fpgaregs w 0
</pre>

====16 bits write====
<pre class="apf">
# fpgaregs w <address> <value>
</pre>

Where <value> is hexadecimal value to write.

====32 bits read====
<pre class="apf">
# fpgaregs l <address>
</pre>

====32 bits write====
<pre class="apf">
# fpgaregs l <address> <value>
</pre>

== the mmap problem ==

{{Note| This problem is corrected with latest Toolchains compilation options}}

First of all, you need to get a file descriptor for ''/dev/mem'' using the ''open()'' function
<source lang="c">
ffpga=open("/dev/mem",O_RDWR|O_SYNC);
</source>
Now you have a valid file descriptor to access your FPGA.

The O_SYNC option is recommended to avoid Linux to cache the content of /dev/mem and delay any modification done in this file.

To access fpga register, fpgaregs use the ''mmap()'' system call :

<source lang="c">
void * ptr_fpga;
ptr_fpga = mmap (0, 8192, PROT_READ|PROT_WRITE, MAP_SHARED, ffpga, FPGA_ADDRESS);
</source>

Thanks to this function, fpga registers are accessible directly on memory with pointer ptr_fpga. To read and write in 16bits or in 32 bits we will cast the pointer value in ''unsigned short'' or ''unsigned int'' :

'''16bits'''
''write''
<source lang="c">
*(unsigned short*)(ptr_fpga+(address)) = (unsigned short)value;
</source>
''read''
<source lang="c">
value = *(unsigned short*)(ptr_fpga+(address));
</source>

'''32 bits'''
''write''
<source lang="c">
*(unsigned int*)(ptr_fpga+(address)) = (unsigned short)value;
</source>

''read''
<source lang="c">
value = *(unsigned int*)(ptr_fpga+(address));
</source>

=== The problem ===

By default, if the specific ''arm920t'' target is not specified, ''arm-linux-gcc'' will try to generate compatible read/write for all ARM9 model when it access register in 16bits. Indeed it seems that not all ARM9 have 16bits read/write capabilities (''ldrh'' asm instruction).

As the interface between i.MXL and FPGA on APF9328 has no 8bits read/write capabilities, each 8 bits access is recognized by the FPGA as a 16bits access. So on each 16bits access of the i.MXL, FPGA will process two 16bits access instead of 1. That is a problem when accessing a FIFO for example.

To avoid this painful problem don't forget the ''-mcpu=arm920t'' option when compiling ''fpgaregs'' for APF9328 and ''-mcpu=arm926ej-s'' for APF27.

==Links==
* http://sources.redhat.com/ml/crossgcc/2005-08/msg00120.html : Explanation of the problem.

FPGA registers access from Linux userspace on APF9328, APF27 SP, APF51 SP and OPOS6UL SP

2026-10-22T09:09:28Z

FabienM: /* Introduction */

[[Category:FPGA]]
[[Category: APF9328]]
[[Category: APF27]]
[[Category: APF51]]
[[Category: OPOS6UL_SP]]

== Introduction ==

For '''APF9328, APF27, APF51 and OPOS6UL_SP''', registers access are done with a memory bus (parallel).
Access through this bus can be made by two methods:
* Using ''fpgaregs'' tool

{{Warning| With defaults wishbone wrappers FPGA accesses are configured for 16bits accesses for [[APF9328]], [[APF27]], [[APF51]] and [[OPOS6UL_SP]]. To make 32bits access, (W)EIM bus configuration and HDL wrappers must be modified.}}

== fpgaregs ==
===Installation===
If the fpgaregs package is not already installed on your APF (''/usr/bin/fpgaregs''), you can select it in the Buildroot menuconfig:
<pre class="host">
$ make menuconfig
</pre>

<pre class="config">
Package Selection for the target --->
[*] Hardware handling / blockdevices and filesystem maintenance --->
[*] fpgaregs
</pre>

<pre class="host">
$ make
</pre>

Then reflash your rootfs or install it manually.

===Usage===

''fpgaregs'' can be used to do read or write accesses (16 or 32 bits wide) to the FPGA, from Linux userspace/console.

====16 bits read====
<pre class="apf">
# fpgaregs w <address>
</pre>

Where <address> is an address relative to FPGA's mapping in hexadecimal value. Example:
<pre class="apf">
# fpgaregs w 0
</pre>

====16 bits write====
<pre class="apf">
# fpgaregs w <address> <value>
</pre>

Where <value> is hexadecimal value to write.

====32 bits read====
<pre class="apf">
# fpgaregs l <address>
</pre>

====32 bits write====
<pre class="apf">
# fpgaregs l <address> <value>
</pre>

== the mmap problem ==

{{Note| This problem is corrected with latest Toolchains compilation options}}

First of all, you need to get a file descriptor for ''/dev/mem'' using the ''open()'' function
<source lang="c">
ffpga=open("/dev/mem",O_RDWR|O_SYNC);
</source>
Now you have a valid file descriptor to access your FPGA.

The O_SYNC option is recommended to avoid Linux to cache the content of /dev/mem and delay any modification done in this file.

To access fpga register, fpgaregs use the ''mmap()'' system call :

<source lang="c">
void * ptr_fpga;
ptr_fpga = mmap (0, 8192, PROT_READ|PROT_WRITE, MAP_SHARED, ffpga, FPGA_ADDRESS);
</source>

Thanks to this function, fpga registers are accessible directly on memory with pointer ptr_fpga. To read and write in 16bits or in 32 bits we will cast the pointer value in ''unsigned short'' or ''unsigned int'' :

'''16bits'''
''write''
<source lang="c">
*(unsigned short*)(ptr_fpga+(address)) = (unsigned short)value;
</source>
''read''
<source lang="c">
value = *(unsigned short*)(ptr_fpga+(address));
</source>

'''32 bits'''
''write''
<source lang="c">
*(unsigned int*)(ptr_fpga+(address)) = (unsigned short)value;
</source>

''read''
<source lang="c">
value = *(unsigned int*)(ptr_fpga+(address));
</source>

=== The problem ===

By default, if the specific ''arm920t'' target is not specified, ''arm-linux-gcc'' will try to generate compatible read/write for all ARM9 model when it access register in 16bits. Indeed it seems that not all ARM9 have 16bits read/write capabilities (''ldrh'' asm instruction).

As the interface between i.MXL and FPGA on APF9328 has no 8bits read/write capabilities, each 8 bits access is recognized by the FPGA as a 16bits access. So on each 16bits access of the i.MXL, FPGA will process two 16bits access instead of 1. That is a problem when accessing a FIFO for example.

To avoid this painful problem don't forget the ''-mcpu=arm920t'' option when compiling ''fpgaregs'' for APF9328 and ''-mcpu=arm926ej-s'' for APF27.

==Links==
* http://sources.redhat.com/ml/crossgcc/2005-08/msg00120.html : Explanation of the problem.

OPOS6UL SP

2026-10-14T08:44:48Z

FabienM: /* FPGA */

[[Category: OPOS6UL_SP]]
[[Category:MainBoards]]
[[Category:Hardware]]

== Description ==

[[File:OPOS6UL_SP.png]]

The OPOS6UL_SP is a [https://en.wikipedia.org/wiki/Single-board_computer Single Board Computer] with a FPGA. This board is mainly pin-to-pin compatible with the APF27. The objective is to replace APF27 with minimum electronic and software refactoring.

Here is a list of the main features:
* Processor: [https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core:i.MX6ULL i.MX6ULL] (i.MX6ULL single A7 @ 800 or 900MHz)
* FPGA: [https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html Spartan6 LX9]

TODO

==Resources==

TODO

==Features list==

* [[OPOS6UL_SP Linux kernel status]]

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
|
=== FPGA ===

* Spartan6 ([[OPOS6UL_SP_Interfaces_description | FPGA Interface description]])

===Video===
====Video Out====
* [[LCD]]
* [[FrameBuffer]]

====Video In====
*[[Camera interface]]

||

===Wired communication===
* [[Uart|UART]]
* [[SPI]]
* [[I2C]]
* [[USB_Host]]
* [[USB_Gadget]]
* [[USB_OTG]]
* [[CAN_bus_Linux_driver|CAN bus]]

||

===Storage===

* [[EMMC OPOS6UL|eMMC]]

===Other===
* [[PWM]]
* [[GPIOlib]]
* [[Linux_Dynamic_Frequency_Scaling|Frequency scaling]]
|}

==Development boards==
* [[OPOS6UL_SPDev]]
* [[APF27Dev]]

OPOS6UL SP

2026-10-14T08:44:31Z

FabienM: /* FPGA */

[[Category: OPOS6UL_SP]]
[[Category:MainBoards]]
[[Category:Hardware]]

== Description ==

[[File:OPOS6UL_SP.png]]

The OPOS6UL_SP is a [https://en.wikipedia.org/wiki/Single-board_computer Single Board Computer] with a FPGA. This board is mainly pin-to-pin compatible with the APF27. The objective is to replace APF27 with minimum electronic and software refactoring.

Here is a list of the main features:
* Processor: [https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6ull-single-core-processor-with-arm-cortex-a7-core:i.MX6ULL i.MX6ULL] (i.MX6ULL single A7 @ 800 or 900MHz)
* FPGA: [https://www.xilinx.com/products/silicon-devices/fpga/spartan-6.html Spartan6 LX9]

TODO

==Resources==

TODO

==Features list==

* [[OPOS6UL_SP Linux kernel status]]

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
|
=== FPGA ===

* [[OPOS6UL_SP_Interfaces_description | FPGA Interface description]]

===Video===
====Video Out====
* [[LCD]]
* [[FrameBuffer]]

====Video In====
*[[Camera interface]]

||

===Wired communication===
* [[Uart|UART]]
* [[SPI]]
* [[I2C]]
* [[USB_Host]]
* [[USB_Gadget]]
* [[USB_OTG]]
* [[CAN_bus_Linux_driver|CAN bus]]

||

===Storage===

* [[EMMC OPOS6UL|eMMC]]

===Other===
* [[PWM]]
* [[GPIOlib]]
* [[Linux_Dynamic_Frequency_Scaling|Frequency scaling]]
|}

==Development boards==
* [[OPOS6UL_SPDev]]
* [[APF27Dev]]

OPOSA5E SP

2026-07-30T08:06:08Z

FabienM: /* FPGA */

[[Category:OPOSA5E_SP]]
[[Category:MainBoards]]
[[Category:Hardware]]
[[Category:Altera]]
[[Category:Agilex5]]
[[Category:FPGA]]

== Description ==

[[File:OPOSA5E_SP_TOP.png]]

[https://www.opossom.com/en/product-oposa5esp/index.html OPOSA5E_SP] is a SoM structured arround an [https://www.altera.com/products/fpga/agilex/5 Agilex5] SoC produced by Altera.

Here is a list of the main features:

=== FPGA ===

* [[OPOSA5E_SP_Interface_description | Interface description]]

File:OPOSA5E SP TOP.png

2026-07-30T08:05:27Z

FabienM:

OPOSA5E SP

2026-07-30T08:05:16Z

FabienM: /* Description */

[[Category:OPOSA5E_SP]]
[[Category:MainBoards]]
[[Category:Hardware]]
[[Category:Altera]]
[[Category:Agilex5]]
[[Category:FPGA]]

== Description ==

[[File:OPOSA5E_SP_TOP.png]]

[https://www.opossom.com/en/product-oposa5esp/index.html OPOSA5E_SP] is a SoM structured arround an [https://www.altera.com/products/fpga/agilex/5 Agilex5] SoC produced by Altera.

=== FPGA ===

* [[OPOSA5E_SP_Interface_description | Interface description]]

Hardware

2026-07-30T08:00:53Z

FabienM: /* APFxx and OPOSxx Systems on Module (SoM) */

==Armadeus Boards==
The following boards are developed by [http://www.armadeus.com Armadeus Systems]. Members of the Armadeus Project association can purchase these products at discount prices. Take a look at the [[Association]] page for details.

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |
=== APFxx and OPOSxx Systems on Module (SoM) ===
* [[APF9328]]: i.MXL based module
* [[APF27]]: i.MX27 based module with Spartan3 FPGA
* [[APF51]]: i.MX51 based module with Spartan6 FPGA
* [[APF28]]: i.MX28 based module
* [[APF6]]: i.MX6 based module
* [[APF6_SP]] : i.MX6 based module with CycloneV FPGA
* [[OPOS6UL]] : i.MX6UL based module
* [[OPOS6UL_NANO]] : i.MX6UL based nano module
* [[OPOS6UL_SP]] : i.MX6ULL based module with a Spartan6 FPGA
* [[OPOS93]]: i.MX93 based module
* [[OPOS93_SP]]: i.MX93 based module with a Trion FPGA
* [[OPOSA5E_SP]]: Agilex5 based module with CPU (HPS) and FPGA included.
* [[Footprints]] : Footprint available for APFxx module
||

=== Baseboards ===
* [[OPOS93SPDev]]: full featured development board for the OPOS93_SP
* [[OPOS93Dev]]: full featured development board for the OPOS93
* [[OPOS6ULDev used with an OPOS6UL_NANO]]: full featured development board of the [[OPOS6UL]], but used with an [[OPOS6UL_NANO]] SOM (needs a SODIMM adapter
* [[OPOS6ULDev]]: full featured development board for the [[OPOS6UL]]
* No more available:
** [[APF9328DevLight]]: low cost development board for the APF9328
** [[APF9328DevFull]]: full featured development board for the APF9328
** [[APF6Dev]]: full featured development board for the APF6
** [[APF28Dev]]: full featured development board for the APF28
** [[APF51Dev]]: full featured development board for the APF51
** [[APF27Dev]]: full featured development board for the APF27 (with several options)
** [[APF27 PPS]]/PPS: network applications development board for the APF27
** [[PPS51]]: network applications development board for the APF51
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Extension Boards ===
* [[Chimei_LW700|LW700AT_Adapt]]: Adapter for the Chimei LW700 TFT LCD
* [[Wireless_extension_board|APW wireless board]]: Add WiFi & Bluetooth & GPS & GSM to your [[APF27Dev]]
* [[SP_VISION]]: Extension with Spartan6 FPGA, for video processing
* No more available:
** [[LQ043_Adapt]]: Adapter for the Sharp LQ043 TFT LCD
** [[MTF-T035|MTF-T035_Adapt]]: Adapter for the Microtips MTF-T035 TFT LCD

||

=== Demo Boards ===
* [[HMS Demo]]: industrial demo platform
|}

==Tools==
* [http://kicad-pcb.org/ Kicad EDA tool]

OPOSA5E SP

2026-07-28T12:36:29Z

FabienM: /* FPGA */

[[Category:OPOSA5E_SP]]
[[Category:MainBoards]]
[[Category:Hardware]]
[[Category:Altera]]
[[Category:Agilex5]]
[[Category:FPGA]]

== Description ==

[https://www.opossom.com/en/product-oposa5esp/index.html OPOSA5E_SP] is a SoM structured arround an [https://www.altera.com/products/fpga/agilex/5 Agilex5] SoC produced by Altera.

=== FPGA ===

* [[OPOSA5E_SP_Interface_description | Interface description]]

OPOSA5E SP

2026-07-28T12:35:36Z

FabienM: Created page with "Category:OPOSA5E_SP Category:MainBoards Category:Hardware Category:Altera Category:Agilex5 Category:FPGA == Description == [https://www.opossom.com/en/product-oposa5esp/index.html OPOSA5E_SP] is a SoM structured arround an [https://www.altera.com/products/fpga/agilex/5 Agilex5] SoC produced by Altera. === FPGA === * Interface description"

OPOSA5E SP Interface description

2026-07-28T12:31:30Z

FabienM: /* Introduction */

[[Category: OPOSA5E_SP]]
[[Category: Agilex5]]
[[Category: FPGA]]

== Introduction ==

[[Using_FPGA| << FPGA general page]]

OPOSA5E SP Interface description

2026-07-28T12:30:02Z

FabienM: Created page with "Category: OPOSA5E_SP Category: Agilex5 Category: FPGA == Introduction =="

[[Category: OPOSA5E_SP]]
[[Category: Agilex5]]
[[Category: FPGA]]

== Introduction ==

Using FPGA

2026-07-28T12:28:17Z

FabienM: /* FPGA Interfaces */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]
* '''OPOSA5E_SP''': [[OPOSA5E_SP Interface description]]

==== Accessing the FPGA address domain from Linux userspace ====
* [[FPGA_registers_access_from_Linux_userspace_on_APF9328,_APF27_SP,_APF51_SP_and_OPOS6UL_SP | APF9328, APF27_SP, APF51_SP and OPOS6UL_SP]]
* [[FPGA_registers_access_from_Linux_userspace_on_APF6_SP | APF6_SP]]
* [[FPGA_registers_access_from_Linux_userspace_on_OPOS93_SP | OPOS93_SP]]

==== Accessing the FPGA address domain from Linux kernel ====

* [[FPGA_registers_access_from_Linux_kernel_on_OPOS93_SP | OPOS93_SP]]

| width="50%" |

=== FPGA designing on Armadeus platforms ===

These examples give the basis to make VHDL design for FPGA.

*'''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''':
** [[Simple blinking LED | LED]]
** [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
*'''APF6_SP'''
** [[APF6_SP_FPGA_designing | FPGA designing]]
*'''OPOS93_SP'''
** [[OPOS93_SP_FPGA_designing | FPGA designing]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Configuring Armadeus platform's FPGA ===

'''Platforms'''
* '''APF9328''', '''APF27''', '''APF51''', '''OPOS6UL_SP''': [[APF9328_APF27_APF51_OPOS6UL_SP FPGA_configuration | Configure APF9328, APF27, APF51 or OPOS6UL_SP FPGA]]
* '''APF6_SP''': [[APF6_SP_FPGA_configuration | Configure APF6_SP FPGA]]
* '''OPOS93_SP''': [[OPOS93_SP_FPGA_configuration | Configure OPOS93_SP FPGA]]

'''Tools'''

* [[FPGA_loader | FPGA loader Linux driver]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Efinix'''
* [[Efinity]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

Network File System configuration

2026-07-27T13:50:43Z

FabienM: /* Portmap/RPCbind */

==Introduction==

On this page, you will find usefull informations to configure NFS ([[wikipedia:Network_File_System_(protocol)|Network File System]]) on your Host and your Target.

==NFS server on your development Host==

===Installation===
* On Fedora, NFS is part of your distribution so you normally don't need to install it.
* On Ubuntu/Kubuntu:
$ sudo apt-get install nfs-kernel-server
* On OpenSUSE:
$ sudo zypper install yast2-nfs-server
* On Gentoo:
# emerge -av nfs-utils

You can also take a look at the [https://wiki.gentoo.org/wiki/Nfs-utils gentoo wiki]
===Configuration===
====/etc/exports====
* You have to declare the directory where you're going to store the files you want to share accross the network. For that you have to modify the '''/etc/exports''' file with (for example):
<pre class="host">
$ sudo vim /etc/exports
</pre>
and add it (at the end of the file):
<source lang="bash">
...
# Directory for Armadeus:
/local/export 192.168.0.0/255.255.255.0(ro,no_root_squash,sync)
...
</source>
:In that case your Host will authorize all client from the subnet 192.168.*.* to access ''/local/export'' in '''read only''' mode. If you want read/write access from your APF to your exported dir, then replace ''ro'' with ''rw''. 
* In order to use the same folder through TFTP and NFS, using the default U-Boot scripts for example, it recommended to export your /tftpboot folder as well:
<source lang="bash">
...
# Directory for Armadeus:
/local/export 192.168.0.0/255.255.255.0(ro,no_root_squash,sync)
/tftpboot 192.168.0.0/255.255.255.0(ro,no_root_squash,sync)
...
</source>
* If not existing, create your export directory (for example):
<pre class="host">
$ sudo mkdir -p /local/export
$ sudo chown -R $USER:$GROUP /local/export/
</pre>

====/etc/hosts====
* You have to declare your APF/OPOS board in the PC hosts list, to fully support NFS access from U-Boot. For such purpose you have to update the ''/etc/hosts'' file with your preferred editor (as root):
<pre class="host">
$ sudo vim /etc/hosts
</pre>
and add the IP address of your board after the localhost definition for example :
<source lang="bash">
127.0.0.1 localhost
192.168.0.10 apf
...
</source>

====Restart of NFS server====
{| border="1" cellpadding="5" cellspacing="0" summary="Restart of NFS server depending on your distribution"
|- style="background:#efefef;"
! '''On Fedora''' || '''On Ubuntu/Kubuntu/debian''' || '''On OpenSUSE''' || '''On Gentoo'''
|-

|<pre class="host">
# /sbin/service nfs restart
</pre>
Next time you boot, you can check your NFS server status with:
<pre class="host">
# /sbin/service nfs status
</pre>
and if not started then:
<pre class="host">
# /sbin/service nfs start
</pre>

|| <pre class="host">
$ sudo /etc/init.d/nfs-kernel-server restart
</pre>
Next time you boot, you can check your NFS server status with:
''System Settings->System services''
|| <pre class="host">
# /etc/init.d/nfsserver restart
</pre>

|| <pre class="host">
# /etc/init.d/nfs restart
</pre>
|}

==NFS usage on your Armadeus board==

===Mount the NFS partition manually ===
* check if mount point is existing (for example we will take ''/mnt/nfs''):
<pre class="apf">
# ls /mnt
</pre>
* if not existing, create the mount point:
<pre class="apf">
# mkdir -p /mnt/nfs
</pre>
* mount it (for example):
<pre class="apf">
# mount -t nfs 192.168.0.2:/local/export /mnt/nfs
</pre>
Here 192.168.0.2 is your Host IP address and ''/local/export'' the name of your Host directory you want to mount.

{{Note| On some nfs server (for exemple with debian wheezy) there is a warning when we mount nfs partition. But the filesystem is mounted :
<pre class="apf">
# mount /mnt/nfs/
svc: failed to register lockdv1 RPC service (errno 97).
</pre>
}}

===Mount the NFS partition automatically at each boot from FLASH===

* login to your Armadeus board as root
* open the '''/etc/fstab''' file and add this line:
<host-ip>:/<path-to-shared-folder> /mnt/<path-to-mount-folder> nfs hard,intr,rsize=8192,wsize=8192 0 0
example:
192.168.0.2:/local/export /mnt/nfs nfs hard,intr,rsize=8192,wsize=8192 0 0
* check your modification:
<pre class="apf">
# mount /mnt/nfs
</pre>
* reboot your board
<pre class="apf">
# reboot
</pre>
* and enjoy the result
<pre class="apf">
# df
# ls /mnt/nfs
</pre>

When you have a problem, verify that the NFS server is running on the host:
{| border="1" cellpadding="5" cellspacing="0" summary="Status of NFS server depending on your distribution"
|- style="background:#efefef;"
! '''On Fedora''' || '''On Ubuntu/Kubuntu/debian''' || '''On OpenSUSE''' || '''On Gentoo'''
|-

| <pre class="host">
$ /sbin/service nfs status
</pre>

||<pre class="host">
$ /etc/init.d/nfs-kernel-server status
</pre>
||

||
|}

===Boot from NFS===
This boot procedure is usefull to test a modified rootfs and/or a linux kernel keeping safe the original flash memory content of your board.
* on your Host, expand generated rootfs image to your NFS export dir (for example if your NFS export dir is ''/tftpboot'' on your Host) and you want to boot on it using the U-Boot script nfsboot:
<pre class=host>
$ make shell_env
$ source armadeus_env.sh
$ sudo mkdir -p /tftpboot/$ARMADEUS_BOARD_NAME-root/boot
$ sudo tar xvf $ARMADEUS_ROOTFS_TAR -C /tftpboot/$ARMADEUS_BOARD_NAME-root
</pre>
* The copy of the Linux kernel to the NFS ''/boot'' folder, makes possible to also download it with NFS when booting the board:
<pre class=host>
$ sudo cp $ARMADEUS_BINARIES/$ARMADEUS_BOARD_NAME-linux.bin /tftpboot/$ARMADEUS_BOARD_NAME-root/boot/
</pre>
* With recent (3.10+) kernels, you also have to copy the Device Tree blobs:
<pre class=host>
$ sudo mkdir -p /tftpboot/$ARMADEUS_BOARD_NAME-root/boot/dtbs
$ sudo cp $ARMADEUS_BINARIES/*.dtb /tftpboot/$ARMADEUS_BOARD_NAME-root/boot/dtbs/
</pre>

* On your board, in U-Boot, check if the ''rootpath'' envt variable is set accordingly:
<pre class="apf">
BIOS> printenv rootpath
</pre>
* If not, then set it (by default U-boot is configured to use the following path ''/tftpboot/apfXXXX-root'') where apfXXXX may be apf9328, apf27, apf28, apf51, apf6:
<pre class="apf">
BIOS> setenv rootpath /tftpboot/${board_name}-root
</pre>
* save it:
<pre class="apf">
BIOS> saveenv
</pre>
* then boot with:
<pre class="apf">
BIOS> run nfsboot
</pre>

===Summary of the required Packages:===
* portmap (Buildroot)
* nfs (busybox)
* nfs support (Linux, activated by default in Armadeus configuration)

==Troubleshooting==

===RPC: Program not registered===
* If ''nfsd'' and ''mountd'' daemons are not running on your Host, then you will get a message like:
<pre class="apf">
mount: RPC: Program not registered
</pre>
* In that case, restart the NFS service on your Host (see [[Network_File_System_configuration#Restart_of_NFS_server|above]]).

===Portmap/RPCbind===
* To successfully mount a NFS drive, ''portmap''/''rpcbind'' daemon should be running on your APF/OPOS, if not, system will hang during some minutes when you launch the mount !!
To check if ''portmap''/''rpcbind'' is running, look at the running processes:
<pre class="apf">
# ps faux
</pre>
If ''portmap/rpcbind'' is not listed, then launch it manually or install it:
<pre class="apf"
# /etc/init.d/S13portmap
</pre>
* Note: ''portmap'' is obsolete since 2017

===Connection refused===
* If you get this on your APF when trying to mount:
<pre class="apf">
mount: mounting 192.168.0.2:/local/export on /mnt/nfs/ failed: Connection refused
</pre>
* then your kernel might need some extra options:
<pre class="apf">
mount -o port=2049,nolock,proto=tcp 192.168.0.2:/local/export /mnt/nfs/
</pre>

=== errno 111 ===

* If you have ''errno 111'' error:
<pre class="apf">
# mount -t nfs 192.168.0.152:/nfsroot /mnt/nfs
[10577.918887] svc: failed to register lockdv1 RPC service (errno 111).
[10577.925392] lockd_up: makesock failed, error=-111
mount: mounting 192.168.0.152:/nfsroot on /mnt/nfs failed: Connection refused
</pre>

* then try version 4 of nfs:
<pre class="apf">
# mount -t nfs -o vers=4 192.168.0.152:/nfsroot /mnt/nfs
</pre>

* or nolock option :
<pre class="apf">
# mount -t nfs -o vers=3,nolock 192.168.0.152:/nfsroot /mnt/nfs
</pre>

===Kernel debug===
* If none of the above workarounds was successful -> no luck ! :-) You can still activate NFS debugging by recompiling your kernel with CONFIG_SUNRPC_DEBUG options and use ''setenv extrabootargs nfsrootdebug'' in U-Boot. And then you dig...

==NFS Server under Windows==
For those who want to use the NFS service on Windows, a small and FREE NFS server is available [http://www.freedownloadscenter.com/Utilities/Misc__Utilities/nfsAxe.html here].

==Links==
* http://www.denx.de/wiki/view/DULG/SystemSetup#Section_4.8.

[[Category:Network]]

Quilt

2026-07-08T13:29:25Z

FabienM:

== Introduction ==
Quilt is a little tool used to manage patches. The project is hosted on [http://savannah.nongnu.org/projects/quilt savannah forge] and can be found in debian [https://packages.debian.org/sid/quilt package repository].

== Using quilt in Armadeus project ==

Quilt is useful when linux kernel or buildroot modification must be done. Because Armadeus use official linux/buildroot sources, each specific modification for our platform must be done with a patch. And patches are versionned on Armadeus gitlab repository in directory buildroot/target/device/armadeus/linux/kernel-patches/ for Linux kernel and in patches/buildroot for buildroot.

=== quiltify.sh ===

To use it under Armadeus Project, a simple script was written to simplify it : ''quiltify.sh''. Launch it from the root project :

<pre class="host">
[ ] $ ./scripts/quiltify.sh
</pre>

Then answer questions (defaults are recommended). For linux kernel, quiltify will rename your source directory and download/patch/compile again the sources.

=== By Hand ===

quiltify is used when patch are stored in Armadeus standard directory. For specific projects, where patches are stored elsewhere it doesn't work. To do this, you can follow this procedure:

* linux-dirclean: linux kernel should be rebuild from ''scratch'' then first we have to cut the branch (in bsp root directory do):
<pre class="host">
$ make linux-dirclean
</pre>
* linux-extract: We have to just extract virgin linux source (don't compile yet):
<pre class="host">
$ make linux-extract
</pre>
* Once extract done, go to linux source directory and add patch one by one :
<pre class="host">
$ cd buildroot/output/build/linux-5.3-rc4/
# Import patches one by one:
$ quilt import /Path/to/personnal/kernel/patches/my_wonderful_patch.patch
# All patches from a directory:
$ quilt import /Path/to/personnal/kernel/patches/*.patch
</pre>

=== Play with quilt ===

Once you done it, you can go to linux sources directory ''buildroot/project_build_armv5te/apf27/linux-2.6.29.6'' then list all patches applied to with quilt command :
<pre class="host">
[ ] $ quilt applied
015-armadeus-logo-add_armadeus-project_tux.patch
016-armadeus-imxfb-add_platform_specific_init_exit_functions.patch
018-armadeus-i2c-imx-add_driver_to_linux_build_system.patch
…
336-armadeus-imxfb-makes_it_compatible_with_arch_imx.patch
337-armadeus-imxfb-add_lcd_clock_def_for_imx_platform.patch
338-denx-mxcgpio-emulates_interrupt_on_both_edges.patch
339-apf27-armadeus-spidev.patch
</pre>

If you want to create a new patch, just use ''new'' quilt command. Then '''before''' modifying Linux file, add it to quilt with ''add'' command.

The file can be modified according to your wish.

Once modification done, you can generate the patch using ''refresh'' command. To add yours patches in the right directory, go to your project root then launch the script with ''export'' command :
<pre class="host">
[ ] $ ./scripts/quiltify.sh export
</pre>

Your patch is now ready to be committed on Armadeus gitlab.

== Documentation ==

The [http://linux.die.net/man/1/quilt man page] of quilt is a good documentation, it's strongly recommended to read it before using it.

OPOS6UL SP Interfaces description

2026-06-09T09:55:40Z

FabienM: /* Pinout */

[[Category: OPOS6UL_SP]]
[[Category: FPGA]]
[[Category: Spartan6]]
[[Category: ISE]]
[[Category: XILINX]]

== Introduction ==

This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule. All description of this bus can be found under the i.MX6UL(L) [https://www.nxp.com/webapp/Download?colCode=IMX6ULRM reference manual] in chapter 21 (page 821).

FPGA used on board is an '''XC6SLX9-2CSG225'''.

== Simplified view ==

[[File:OPOS6UL_SP_EIM_FPGA_INTERFACE.png|600px|center|thumb|'''figure 1''' - ''i.MX6UL(L)-Spartan6 bus description'']]

Normal communication between i.MX6UL(L) processor and Spartan6 fpga is done with black following signals :

* '''EIM_BCLK''' : Clock
* '''EIM_DA[15:0]''': 16bits data and address bus
* '''EIM_LBA (ADV)''': Signal used for data/address muxing
* '''EIM_RW''': Read/Write control signal
* '''EIM_CS0''': Chip select

Gray following signals can be used by EIM (External Interface Memory), but not used in default configuration :

* '''EIM_EB0''': Select byte 0 on bus
* '''EIM_EB1''': Select byte 1 on bus
* '''OE''' : Output enable
* '''EIM_CLK0''': second clock (EIM_ACLK)

Blue following signals are used for FPGA configuration from imx. Some EIM (black) signals are also used for it.

* '''FPGA_INITB''': Initialize FPGA
* '''FPGA_PROGRAM''' : Program (configure) FPGA
* '''FPGA_DONE''': FPGA configuration is done.

== Tutorials ==

* [[opos6ul_sp_fpga_simple_howto | Simple tutorial to make communication]]
== Default configuration on CSx ==

=== Clocks ===

The clock used to clock the FPGA is EIM_BCLK (IO_L1P_CCLK_2(N12) and IO_L29P_GCLK3_2(N8)) and is configured to '''99 MHz'''.

=== Chip Select ===

The EIM memory space is mapped into 128 MB total memory space in the processor
memory. This memory space begin at address '''0x50000000'''.

{| class="wikitable"
! scope="col"| Start address
! scope="col"| End address
! scope="col"| Size
! scope="col"| Name
|-
! scope="row"| 0x5000_0000
| 0x57FF_FFFF
| 128 MB
| EIM (NOR/SRAM)
|}

The total 128 MB of memory can be divided among the EIM four chip selects. See reference manual of i.MX6ULL for more information.

=== Timings ===

==== Read ====

* U-Boot: To read one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
BIOS> md.w 50000000 1
</pre>

* Linux: To read one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
# devmem 0x50000000 16
</pre>
* Bus timings are following :

<wavedrom>
{ signal: [
{ name: "BCLK", wave: "P......" },
{ name: "DA", wave: "x34...x", data: "addr data", node:"..c...d." },
{ name: "ADV", wave: "101...."},
{ name: "RW", wave: "0......"},
{ name: "CS0", wave: "1.0...1"},
{ node:"..a...b." }
],
edge: ['a<-|->b RWSC=4', 'c-a', 'd-b']
}
</wavedrom>

==== Write ====

* U-Boot: To write one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
BIOS> mw.w 50000000 CAFE
</pre>

* Linux: To write one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
# devmem 0x50000000 16 0xCAFE
</pre>
* Bus timings are following :

<wavedrom>
{ signal: [
{ name: "BCLK", wave: "P......" },
{ name: "DA", wave: "x34...x", data: "addr data", node:"..c...d." },
{ name: "ADV", wave: "101...."},
{ name: "RW", wave: "0.1...0"},
{ name: "CS0", wave: "1.0...1"},
{ node:"..a...b." }
],
edge: ['a<-|->b WWSC=4', 'c-a', 'd-b']
}
</wavedrom>

== code & mapping ==
=== Pinout ===

Schematics interfaces is given here :

[[File:Opos6ul_sp_sch_int.jpg]]

UCF example for interface generated by [https://github.com/Martoni/periphondemand POD] is given here :

<pre>
NET "rstgen_syscon00_ext_clk" LOC="N8" | IOSTANDARD=LVCMOS33; # EIM_BCLK
NET "rstgen_syscon00_ext_clk" TNM_NET = "rstgen_syscon00_ext_clk";
TIMESPEC "TS_rstgen_syscon00_ext_clk" = PERIOD "rstgen_syscon00_ext_clk" 10.101 ns HIGH 50 %;
NET "imx6ul_wb16_wrapper00_imx_da<0>" LOC="P11" | IOSTANDARD=LVCMOS33; # EIM_DA0
NET "imx6ul_wb16_wrapper00_imx_cs_n" LOC="R11" | IOSTANDARD=LVCMOS33; # EIM_CS0
NET "imx6ul_wb16_wrapper00_imx_da<1>" LOC="M11" | IOSTANDARD=LVCMOS33; # EIM_DA1
NET "imx6ul_wb16_wrapper00_imx_da<2>" LOC="N11" | IOSTANDARD=LVCMOS33; # EIM_DA2
NET "imx6ul_wb16_wrapper00_imx_da<10>" LOC="R10" | IOSTANDARD=LVCMOS33; # EIM_DA10
NET "imx6ul_wb16_wrapper00_imx_da<11>" LOC="L9" | IOSTANDARD=LVCMOS33; # EIM_DA11
NET "imx6ul_wb16_wrapper00_imx_da<12>" LOC="M10" | IOSTANDARD=LVCMOS33; # EIM_DA12
NET "imx6ul_wb16_wrapper00_imx_da<13>" LOC="M8" | IOSTANDARD=LVCMOS33; # EIM_DA13
NET "imx6ul_wb16_wrapper00_imx_da<14>" LOC="K8" | IOSTANDARD=LVCMOS33; # EIM_DA14
NET "imx6ul_wb16_wrapper00_imx_da<15>" LOC="L8" | IOSTANDARD=LVCMOS33; # EIM_DA15
NET "imx6ul_wb16_wrapper00_imx_adv" LOC="R7" | IOSTANDARD=LVCMOS33; # EIM_LBA
NET "imx6ul_wb16_wrapper00_imx_da<7>" LOC="N6" | IOSTANDARD=LVCMOS33; # EIM_DA7
NET "imx6ul_wb16_wrapper00_imx_rw" LOC="R6" | IOSTANDARD=LVCMOS33; # EIM_RW
NET "imx6ul_wb16_wrapper00_imx_da<3>" LOC="P5" | IOSTANDARD=LVCMOS33; # EIM_DA3
NET "imx6ul_wb16_wrapper00_imx_da<4>" LOC="R5" | IOSTANDARD=LVCMOS33; # EIM_DA4
NET "imx6ul_wb16_wrapper00_imx_da<5>" LOC="L6" | IOSTANDARD=LVCMOS33; # EIM_DA5
NET "imx6ul_wb16_wrapper00_imx_da<6>" LOC="L5" | IOSTANDARD=LVCMOS33; # EIM_DA6
NET "imx6ul_wb16_wrapper00_imx_da<8>" LOC="M5" | IOSTANDARD=LVCMOS33; # EIM_DA8
NET "imx6ul_wb16_wrapper00_imx_da<9>" LOC="N5" | IOSTANDARD=LVCMOS33; # EIM_DA9
NET "irq_mngr00_gls_irq" LOC="P3" | IOSTANDARD=LVCMOS33; # FPGA_INITB
</pre>

==== APF27 OPOS6UL_SP pin correspondance tables ====

<pre>
APF27 | J2 num | OPOS6UL_SP
-----------|--------|-----------------------
IO_L24P_1 | 22 | IO_L37P_M3DQ0_3
IO_L24N_1 | 23 | IO_L37N_M3DQ1_3
IO_L22P_1 | 24 | IO_L40N_M3DQ7_3
-----------|--------|-----------------------
IO_L02N_0 | 26 | IO_L2P_0
IO_L02P_0 | 27 | IO_L2N_0
IO_L04N_0 | 28 | IO_L4P_0
IO_L04P_0 | 29 | IO_L4N_0
IO_L03N_0 | 30 | IO_L6P_0
IO_L03P_0 | 31 | IO_L6N_0
IO_L08N_0 | 32 | IO_L33P_0
IO_L08P_0 | 33 | IO_L33N_0
IO_L10N_0 | 34 | IO_L35P_GCLK17_0
IO_L10P_0 | 35 | IO_L35N_GCLK16_0
IO_L12N_0 | 36 | IO_L37P_GCLK13_0
IO_L12P_0 | 37 | IO_L37N_GCLK12_0
IO_L15N_0 | 38 | IO_L63P_SCP7_0
IO_L15P_0 | 39 | IO_L63N_SCP6_0
IO_L18N_0 | 40 | IO_L65P_SCP3_0
IO_L18P_0 | 41 | IO_L65N_SCP2_0
-----------|--------|-----------------------
IO_L24P_3 | 43 | IO_L1P_A25_1
IO_L23P_3 | 44 | IO_L1N_A24_VREF_1
IO_L22N_3 | 45 | IO_L33P_A15_M1A10_1
IO_L20N_3 | 46 | IO_L33N_A14_M1A4_1
IO_L20P_3 | 47 | IO_L37P_A7_M1A0_1
IO_L12P_3 | 48 | IO_L37N_A6_M1A1_1
IO_L15N_3 | 49 | IO_L39P_M1A3_1
IO_L14N_3 | 50 | IO_L39N_M1ODT_1
IO_L11N_3 | 51 | IO_L41P_GCLK9_IRDY1_M1RASN_1
IO_L08N_3 | 52 | IO_L41N_GCLK8_M1CASN_1
IO_L08P_3 | 53 | IO_L43P_GCLK5_M1DQ4_1
IO_L03N_3 | 54 | IO_L43N_GCLK4_M1DQ5_1
IO_L03P_3 | 55 | IO_L45P_A1_M1LDQS_1
IO_L01N_3 | 56 | IO_L45N_A0_M1LDQSN_1
-----------|--------|-----------------------
IO_L20N_1 | 99 | IO_L38P_M3DQ2_3
IO_L20P_1 | 98 | IO_L38N_M3DQ3_3
IO_L23N_1 | 97 | IO_L39P_M3LDQS_3
IO_L23P_1 | 96 | IO_L39N_M3LDQSN_3
IO_L22N_1 | 95 | IO_L40P_M3DQ6_3
-----------|--------|-----------------------
IO_L01N_0 | 91 | IO_L3P_0
IO_L01P_0 | 90 | IO_L3N_0
IO_L07N_0 | 89 | IO_L5P_0_NOTLX4
IO_L07P_0 | 88 | IO_L5N_0_NOTLX4
IO_L09N_0 | 87 | IO_L7P_0_NOTLX4
IO_L09P_0 | 86 | IO_L7N_0_NOTLX4
IO_L11N_0 | 85 | IO_L34P_GCLK19_0
IO_L11P_0 | 84 | IO_L34N_GCLK18_0
IO_L16N_0 | 83 | IO_L36P_GCLK15_0
IO_L16P_0 | 82 | IO_L36N_GCLK14_0
IO_L17N_0 | 81 | IO_L38P_0_NOTLX4
IO_L17P_0 | 80 | IO_L38N_VREF_0_NOTLX4
IO_L19N_0 | 79 | IO_L40P_0
IO_L19P_0 | 78 | IO_L40N_0
-----------|--------|-----------------------
IP_L25N_3 | 75 | IO_L38P_A5_M1CLK_1
IO_L24N_3 | 74 | IO_L38N_A4_M1CLKN_1
IO_L23N_3 | 73 | IO_L40P_GCLK11_M1A5_1
IO_L22P_3 | 72 | IO_L40N_GCLK10_M1A6_1
IO_L12N_3 | 71 | IO_L42P_GCLK7_M1UDM_1
IO_L15P_3 | 70 | IO_L42N_GCLK6_TRDY1_M1LDM_1
IO_L14P_3 | 69 | IO_L44P_A3_M1DQ6_1
IO_L11P_3 | 68 | IO_L44N_A2_M1DQ7_1
IO_L04N_3 | 67 | IO_L46P_FCS_B_M1DQ2_1
IO_L02P_3 | 66 | IO_L46N_FOE_B_M1DQ3_1
IO_L02N_3 | 65 | IO_L47P_FWE_B_M1DQ0_1
IO_L01P_3 | 64 | IO_L47N_LDC_M1DQ1_1
-----------|--------|-----------------------
</pre>

=== Simulation model ===

Some simulation model has been written to test eim in VHDL and in python with cocotb.

==== VHDL ====

imx_read and imx_write simulation fonctions are included in POD (Peripheral On Demand) library. Available in [https://github.com/Martoni/pod_lib/blob/master/platforms/opos6ulsp/simulation/opos6ul_test_pkg.vhd platform/opos6ulsp] directory.

==== Cocotb ====

It's possible to simulate eim access with [https://cocotb.readthedocs.io/en/latest/introduction.html cocotb] module named [https://github.com/Martoni/cocotbext-imxeim cocotbext-imxeim].

=== HDL bus wrapper ===

Bus wrapper has been written in VHDL and chisel to convert EIM protocol to Wishbone bus protocol.

==== VHDL ====

A 16 bits multiplexed EIM to 16bits wishbone master bus is available in [https://github.com/Martoni/periphondemand POD] library. The VHDL sources are available following [https://github.com/Martoni/pod_lib/blob/master/library/wrappers/imx6ul_wb16_wrapper/hdl/imx6ul_wb16_wrapper.vhd this link].

==== Chisel ====

A chisel package is available in module [https://github.com/Martoni/ChisArmadeus chisArmadeus] to drive Wishbone master bus with EIM bus [https://github.com/Martoni/ChisArmadeus/blob/master/src/main/scala/chisarmadeus/op6sp/op6sp.scala here].

=== FPGA Interrupt ===

To generate an IRQ from the FPGA to the i.MX, the pin FPGA_INITB is used by default. It correspond to [[GPIOlib#Datasheet_GPIO_number_correspondance | GPIO4_IO16]] on i.MX.

=== FPGA J2 connector mapping ===

Mapping of FPGA pin is given in following [[op6spJ2pinout | csv file]].

== FPGA configuration protocol ==

<TODO>

== Links ==

* [https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf i.MX6UL(L) reference manual] (PDF chapter 21 page 821)
* [https://www.nxp.com/docs/en/data-sheet/IMX6ULLIEC.pdf i.MX6UL(L) Datasheet] (PDF)
* [https://www.xilinx.com/support/documentation/user_guides/ug380.pdf Spartan6 configuration] (PDF)
* [https://github.com/Martoni/pod_lib/tree/master/platforms/opos6ulsp Peripheral On Demand configuration files]

[[Using_FPGA| << FPGA general page]]

OPOS6UL SP Interfaces description

2026-06-09T09:34:14Z

FabienM: /* Pinout */

[[Category: OPOS6UL_SP]]
[[Category: FPGA]]
[[Category: Spartan6]]
[[Category: ISE]]
[[Category: XILINX]]

== Introduction ==

This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule. All description of this bus can be found under the i.MX6UL(L) [https://www.nxp.com/webapp/Download?colCode=IMX6ULRM reference manual] in chapter 21 (page 821).

FPGA used on board is an '''XC6SLX9-2CSG225'''.

== Simplified view ==

[[File:OPOS6UL_SP_EIM_FPGA_INTERFACE.png|600px|center|thumb|'''figure 1''' - ''i.MX6UL(L)-Spartan6 bus description'']]

Normal communication between i.MX6UL(L) processor and Spartan6 fpga is done with black following signals :

* '''EIM_BCLK''' : Clock
* '''EIM_DA[15:0]''': 16bits data and address bus
* '''EIM_LBA (ADV)''': Signal used for data/address muxing
* '''EIM_RW''': Read/Write control signal
* '''EIM_CS0''': Chip select

Gray following signals can be used by EIM (External Interface Memory), but not used in default configuration :

* '''EIM_EB0''': Select byte 0 on bus
* '''EIM_EB1''': Select byte 1 on bus
* '''OE''' : Output enable
* '''EIM_CLK0''': second clock (EIM_ACLK)

Blue following signals are used for FPGA configuration from imx. Some EIM (black) signals are also used for it.

* '''FPGA_INITB''': Initialize FPGA
* '''FPGA_PROGRAM''' : Program (configure) FPGA
* '''FPGA_DONE''': FPGA configuration is done.

== Tutorials ==

* [[opos6ul_sp_fpga_simple_howto | Simple tutorial to make communication]]
== Default configuration on CSx ==

=== Clocks ===

The clock used to clock the FPGA is EIM_BCLK (IO_L1P_CCLK_2(N12) and IO_L29P_GCLK3_2(N8)) and is configured to '''99 MHz'''.

=== Chip Select ===

The EIM memory space is mapped into 128 MB total memory space in the processor
memory. This memory space begin at address '''0x50000000'''.

{| class="wikitable"
! scope="col"| Start address
! scope="col"| End address
! scope="col"| Size
! scope="col"| Name
|-
! scope="row"| 0x5000_0000
| 0x57FF_FFFF
| 128 MB
| EIM (NOR/SRAM)
|}

The total 128 MB of memory can be divided among the EIM four chip selects. See reference manual of i.MX6ULL for more information.

=== Timings ===

==== Read ====

* U-Boot: To read one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
BIOS> md.w 50000000 1
</pre>

* Linux: To read one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
# devmem 0x50000000 16
</pre>
* Bus timings are following :

<wavedrom>
{ signal: [
{ name: "BCLK", wave: "P......" },
{ name: "DA", wave: "x34...x", data: "addr data", node:"..c...d." },
{ name: "ADV", wave: "101...."},
{ name: "RW", wave: "0......"},
{ name: "CS0", wave: "1.0...1"},
{ node:"..a...b." }
],
edge: ['a<-|->b RWSC=4', 'c-a', 'd-b']
}
</wavedrom>

==== Write ====

* U-Boot: To write one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
BIOS> mw.w 50000000 CAFE
</pre>

* Linux: To write one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
# devmem 0x50000000 16 0xCAFE
</pre>
* Bus timings are following :

<wavedrom>
{ signal: [
{ name: "BCLK", wave: "P......" },
{ name: "DA", wave: "x34...x", data: "addr data", node:"..c...d." },
{ name: "ADV", wave: "101...."},
{ name: "RW", wave: "0.1...0"},
{ name: "CS0", wave: "1.0...1"},
{ node:"..a...b." }
],
edge: ['a<-|->b WWSC=4', 'c-a', 'd-b']
}
</wavedrom>

== code & mapping ==
=== Pinout ===

Schematics interfaces is given here :

[[File:Opos6ul_sp_sch_int.jpg]]

UCF example for interface generated by [https://github.com/Martoni/periphondemand POD] is given here :

<pre>
NET "rstgen_syscon00_ext_clk" LOC="N8" | IOSTANDARD=LVCMOS33; # EIM_BCLK
NET "rstgen_syscon00_ext_clk" TNM_NET = "rstgen_syscon00_ext_clk";
TIMESPEC "TS_rstgen_syscon00_ext_clk" = PERIOD "rstgen_syscon00_ext_clk" 10.101 ns HIGH 50 %;
NET "imx6ul_wb16_wrapper00_imx_da<0>" LOC="P11" | IOSTANDARD=LVCMOS33; # EIM_DA0
NET "imx6ul_wb16_wrapper00_imx_cs_n" LOC="R11" | IOSTANDARD=LVCMOS33; # EIM_CS0
NET "imx6ul_wb16_wrapper00_imx_da<1>" LOC="M11" | IOSTANDARD=LVCMOS33; # EIM_DA1
NET "imx6ul_wb16_wrapper00_imx_da<2>" LOC="N11" | IOSTANDARD=LVCMOS33; # EIM_DA2
NET "imx6ul_wb16_wrapper00_imx_da<10>" LOC="R10" | IOSTANDARD=LVCMOS33; # EIM_DA10
NET "imx6ul_wb16_wrapper00_imx_da<11>" LOC="L9" | IOSTANDARD=LVCMOS33; # EIM_DA11
NET "imx6ul_wb16_wrapper00_imx_da<12>" LOC="M10" | IOSTANDARD=LVCMOS33; # EIM_DA12
NET "imx6ul_wb16_wrapper00_imx_da<13>" LOC="M8" | IOSTANDARD=LVCMOS33; # EIM_DA13
NET "imx6ul_wb16_wrapper00_imx_da<14>" LOC="K8" | IOSTANDARD=LVCMOS33; # EIM_DA14
NET "imx6ul_wb16_wrapper00_imx_da<15>" LOC="L8" | IOSTANDARD=LVCMOS33; # EIM_DA15
NET "imx6ul_wb16_wrapper00_imx_adv" LOC="R7" | IOSTANDARD=LVCMOS33; # EIM_LBA
NET "imx6ul_wb16_wrapper00_imx_da<7>" LOC="N6" | IOSTANDARD=LVCMOS33; # EIM_DA7
NET "imx6ul_wb16_wrapper00_imx_rw" LOC="R6" | IOSTANDARD=LVCMOS33; # EIM_RW
NET "imx6ul_wb16_wrapper00_imx_da<3>" LOC="P5" | IOSTANDARD=LVCMOS33; # EIM_DA3
NET "imx6ul_wb16_wrapper00_imx_da<4>" LOC="R5" | IOSTANDARD=LVCMOS33; # EIM_DA4
NET "imx6ul_wb16_wrapper00_imx_da<5>" LOC="L6" | IOSTANDARD=LVCMOS33; # EIM_DA5
NET "imx6ul_wb16_wrapper00_imx_da<6>" LOC="L5" | IOSTANDARD=LVCMOS33; # EIM_DA6
NET "imx6ul_wb16_wrapper00_imx_da<8>" LOC="M5" | IOSTANDARD=LVCMOS33; # EIM_DA8
NET "imx6ul_wb16_wrapper00_imx_da<9>" LOC="N5" | IOSTANDARD=LVCMOS33; # EIM_DA9
NET "irq_mngr00_gls_irq" LOC="P3" | IOSTANDARD=LVCMOS33; # FPGA_INITB
</pre>

- APF27 OPOS6UL_SP pin correspondance tables

<pre>
</pre>

=== Simulation model ===

Some simulation model has been written to test eim in VHDL and in python with cocotb.

==== VHDL ====

imx_read and imx_write simulation fonctions are included in POD (Peripheral On Demand) library. Available in [https://github.com/Martoni/pod_lib/blob/master/platforms/opos6ulsp/simulation/opos6ul_test_pkg.vhd platform/opos6ulsp] directory.

==== Cocotb ====

It's possible to simulate eim access with [https://cocotb.readthedocs.io/en/latest/introduction.html cocotb] module named [https://github.com/Martoni/cocotbext-imxeim cocotbext-imxeim].

=== HDL bus wrapper ===

Bus wrapper has been written in VHDL and chisel to convert EIM protocol to Wishbone bus protocol.

==== VHDL ====

A 16 bits multiplexed EIM to 16bits wishbone master bus is available in [https://github.com/Martoni/periphondemand POD] library. The VHDL sources are available following [https://github.com/Martoni/pod_lib/blob/master/library/wrappers/imx6ul_wb16_wrapper/hdl/imx6ul_wb16_wrapper.vhd this link].

==== Chisel ====

A chisel package is available in module [https://github.com/Martoni/ChisArmadeus chisArmadeus] to drive Wishbone master bus with EIM bus [https://github.com/Martoni/ChisArmadeus/blob/master/src/main/scala/chisarmadeus/op6sp/op6sp.scala here].

=== FPGA Interrupt ===

To generate an IRQ from the FPGA to the i.MX, the pin FPGA_INITB is used by default. It correspond to [[GPIOlib#Datasheet_GPIO_number_correspondance | GPIO4_IO16]] on i.MX.

=== FPGA J2 connector mapping ===

Mapping of FPGA pin is given in following [[op6spJ2pinout | csv file]].

== FPGA configuration protocol ==

<TODO>

== Links ==

* [https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf i.MX6UL(L) reference manual] (PDF chapter 21 page 821)
* [https://www.nxp.com/docs/en/data-sheet/IMX6ULLIEC.pdf i.MX6UL(L) Datasheet] (PDF)
* [https://www.xilinx.com/support/documentation/user_guides/ug380.pdf Spartan6 configuration] (PDF)
* [https://github.com/Martoni/pod_lib/tree/master/platforms/opos6ulsp Peripheral On Demand configuration files]

[[Using_FPGA| << FPGA general page]]

OPOS93 SP

2025-09-23T12:59:12Z

FabienM:

[[Category: OPOS93_SP]]
[[Category:MainBoards]]
[[Category:Hardware]]
[[Category:Efinix]]
[[Category:Trion]]
[[Category:FPGA]]

== Description ==

[https://www.opossom.com/english/product-opos93sp/index.html OPOS93SP] is a SoM derivated from [https://www.opossom.com/english/product-opos93sp/index.html OPOS93] with a FPGA [https://www.efinixinc.com/shop/t20.php Trion T20] produced by Efinix.

=== FPGA ===

* [[OPOS93_SP_Interfaces_description | Interface description]]

OPOS93 SP

2025-09-23T12:57:40Z

FabienM: /* FPGA */

== Description ==

[https://www.opossom.com/english/product-opos93sp/index.html OPOS93SP] is a SoM derivated from [https://www.opossom.com/english/product-opos93sp/index.html OPOS93] with a FPGA [https://www.efinixinc.com/shop/t20.php Trion T20] produced by Efinix.

=== FPGA ===

* [[OPOS93_SP_Interfaces_description | Interface description]]

OPOS93 SP

2025-09-23T12:57:27Z

FabienM: Created page with "== Description == [https://www.opossom.com/english/product-opos93sp/index.html OPOS93SP] is a SoM derivated from [https://www.opossom.com/english/product-opos93sp/index.html OPOS93] with a FPGA [https://www.efinixinc.com/shop/t20.php Trion T20] produced by Efinix. === FPGA === * Trion T20"

Hardware

2025-09-23T12:47:25Z

FabienM: /* Baseboards */

==Armadeus Boards==
The following boards are developed by [http://www.armadeus.com Armadeus Systems]. Members of the Armadeus Project association can purchase these products at discount prices. Take a look at the [[Association]] page for details.

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |
=== APFxx and OPOSxx Systems on Module (SoM) ===
* [[APF9328]]: i.MXL based module
* [[APF27]]: i.MX27 based module with Spartan3 FPGA
* [[APF51]]: i.MX51 based module with Spartan6 FPGA
* [[APF28]]: i.MX28 based module
* [[APF6]]: i.MX6 based module
* [[APF6_SP]] : i.MX6 based module with CycloneV FPGA
* [[OPOS6UL]] : i.MX6UL based module
* [[OPOS6UL_NANO]] : i.MX6UL based nano module
* [[OPOS6UL_SP]] : i.MX6ULL based module with a Spartan6 FPGA
* [[OPOS93]]: i.MX93 based module
* [[OPOS93_SP]]: i.MX93 based module with a Trion FPGA
* [[Footprints]] : Footprint available for APFxx module
||

=== Baseboards ===
* [[OPOS93SPDev]]: full featured development board for the OPOS93_SP
* [[OPOS93Dev]]: full featured development board for the OPOS93
* [[OPOS6ULDev used with an OPOS6UL_NANO]]: full featured development board of the [[OPOS6UL]], but used with an [[OPOS6UL_NANO]] SOM (needs a SODIMM adapter
* [[OPOS6ULDev]]: full featured development board for the [[OPOS6UL]]
* No more available:
** [[APF9328DevLight]]: low cost development board for the APF9328
** [[APF9328DevFull]]: full featured development board for the APF9328
** [[APF6Dev]]: full featured development board for the APF6
** [[APF28Dev]]: full featured development board for the APF28
** [[APF51Dev]]: full featured development board for the APF51
** [[APF27Dev]]: full featured development board for the APF27 (with several options)
** [[APF27 PPS]]/PPS: network applications development board for the APF27
** [[PPS51]]: network applications development board for the APF51
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Extension Boards ===
* [[Chimei_LW700|LW700AT_Adapt]]: Adapter for the Chimei LW700 TFT LCD
* [[Wireless_extension_board|APW wireless board]]: Add WiFi & Bluetooth & GPS & GSM to your [[APF27Dev]]
* [[SP_VISION]]: Extension with Spartan6 FPGA, for video processing
* No more available:
** [[LQ043_Adapt]]: Adapter for the Sharp LQ043 TFT LCD
** [[MTF-T035|MTF-T035_Adapt]]: Adapter for the Microtips MTF-T035 TFT LCD

||

=== Demo Boards ===
* [[HMS Demo]]: industrial demo platform
|}

==Tools==
* [http://kicad-pcb.org/ Kicad EDA tool]

Hardware

2025-09-23T12:46:13Z

FabienM: /* Baseboards */

==Armadeus Boards==
The following boards are developed by [http://www.armadeus.com Armadeus Systems]. Members of the Armadeus Project association can purchase these products at discount prices. Take a look at the [[Association]] page for details.

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |
=== APFxx and OPOSxx Systems on Module (SoM) ===
* [[APF9328]]: i.MXL based module
* [[APF27]]: i.MX27 based module with Spartan3 FPGA
* [[APF51]]: i.MX51 based module with Spartan6 FPGA
* [[APF28]]: i.MX28 based module
* [[APF6]]: i.MX6 based module
* [[APF6_SP]] : i.MX6 based module with CycloneV FPGA
* [[OPOS6UL]] : i.MX6UL based module
* [[OPOS6UL_NANO]] : i.MX6UL based nano module
* [[OPOS6UL_SP]] : i.MX6ULL based module with a Spartan6 FPGA
* [[OPOS93]]: i.MX93 based module
* [[OPOS93_SP]]: i.MX93 based module with a Trion FPGA
* [[Footprints]] : Footprint available for APFxx module
||

=== Baseboards ===
* [[OPOS6ULDev used with an OPOS6UL_NANO]]: full featured development board of the [[OPOS6UL]], but used with an [[OPOS6UL_NANO]] SOM (needs a SODIMM adapter
* [[OPOS6ULDev]]: full featured development board for the [[OPOS6UL]]
* No more available:
** [[APF9328DevLight]]: low cost development board for the APF9328
** [[APF9328DevFull]]: full featured development board for the APF9328
** [[APF6Dev]]: full featured development board for the APF6
** [[APF28Dev]]: full featured development board for the APF28
** [[APF51Dev]]: full featured development board for the APF51
** [[APF27Dev]]: full featured development board for the APF27 (with several options)
** [[APF27 PPS]]/PPS: network applications development board for the APF27
** [[PPS51]]: network applications development board for the APF51
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Extension Boards ===
* [[Chimei_LW700|LW700AT_Adapt]]: Adapter for the Chimei LW700 TFT LCD
* [[Wireless_extension_board|APW wireless board]]: Add WiFi & Bluetooth & GPS & GSM to your [[APF27Dev]]
* [[SP_VISION]]: Extension with Spartan6 FPGA, for video processing
* No more available:
** [[LQ043_Adapt]]: Adapter for the Sharp LQ043 TFT LCD
** [[MTF-T035|MTF-T035_Adapt]]: Adapter for the Microtips MTF-T035 TFT LCD

||

=== Demo Boards ===
* [[HMS Demo]]: industrial demo platform
|}

==Tools==
* [http://kicad-pcb.org/ Kicad EDA tool]

Hardware

2025-08-25T08:32:18Z

FabienM: /* APFxx and OPOSxx Systems on Module (SoM) */

==Armadeus Boards==
The following boards are developed by [http://www.armadeus.com Armadeus Systems]. Members of the Armadeus Project association can purchase these products at discount prices. Take a look at the [[Association]] page for details.

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |
=== APFxx and OPOSxx Systems on Module (SoM) ===
* [[APF9328]]: i.MXL based module
* [[APF27]]: i.MX27 based module with Spartan3 FPGA
* [[APF51]]: i.MX51 based module with Spartan6 FPGA
* [[APF28]]: i.MX28 based module
* [[APF6]]: i.MX6 based module
* [[APF6_SP]] : i.MX6 based module with CycloneV FPGA
* [[OPOS6UL]] : i.MX6UL based module
* [[OPOS6UL_NANO]] : i.MX6UL based nano module
* [[OPOS6UL_SP]] : i.MX6ULL based module with a Spartan6 FPGA
* [[OPOS93]]: i.MX93 based module
* [[OPOS93_SP]]: i.MX93 based module with a Trion FPGA
* [[Footprints]] : Footprint available for APFxx module
||

=== Baseboards ===
* [[OPOS6ULDev used with an OPOS6UL_NANO]]: full featured development board of the [[OPOS6UL]], but used with an [[OPOS6UL_NANO]] SOM (needs a SODIMM adapter
* [[OPOS6ULDev]]: full featured development board for the [[OPOS6UL]]
* [[APF6Dev]]: full featured development board for the APF6
* [[APF28Dev]]: full featured development board for the APF28
* [[APF51Dev]]: full featured development board for the APF51
* [[APF27Dev]]: full featured development board for the APF27 (with several options)
* [[APF27 PPS]]/PPS: network applications development board for the APF27
* [[PPS51]]: network applications development board for the APF51
* No more available:
** [[APF9328DevLight]]: low cost development board for the APF9328
** [[APF9328DevFull]]: full featured development board for the APF9328
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Extension Boards ===
* [[Chimei_LW700|LW700AT_Adapt]]: Adapter for the Chimei LW700 TFT LCD
* [[Wireless_extension_board|APW wireless board]]: Add WiFi & Bluetooth & GPS & GSM to your [[APF27Dev]]
* [[SP_VISION]]: Extension with Spartan6 FPGA, for video processing
* No more available:
** [[LQ043_Adapt]]: Adapter for the Sharp LQ043 TFT LCD
** [[MTF-T035|MTF-T035_Adapt]]: Adapter for the Microtips MTF-T035 TFT LCD

||

=== Demo Boards ===
* [[HMS Demo]]: industrial demo platform
|}

==Tools==
* [http://kicad-pcb.org/ Kicad EDA tool]

OPOS93

2025-08-25T08:29:01Z

FabienM: /* Description */

[[Category: OPOS93]]

{{Under_Construction}}

==Description==

The [https://www.opossom.com/english/product-opos93/index.html OPOS93] is a high-end [https://en.wikipedia.org/wiki/Single-board_computer Single Board Computer] targeted for advanced GUI, intensive AI computation and extended connectivity.

OPOS93

2025-08-25T08:28:51Z

FabienM: Created page with "Category: OPOS93 {{Under_Construction}} ==Description== The[https://www.opossom.com/english/product-opos93/index.html OPOS93] is a high-end [https://en.wikipedia.org/wiki/Single-board_computer Single Board Computer] targeted for advanced GUI, intensive AI computation and extended connectivity."

[[Category: OPOS93]]

{{Under_Construction}}

==Description==

The[https://www.opossom.com/english/product-opos93/index.html OPOS93] is a high-end [https://en.wikipedia.org/wiki/Single-board_computer Single Board Computer] targeted for advanced GUI, intensive AI computation and extended connectivity.

OPOS93 SP Interfaces description

2025-04-10T06:09:10Z

FabienM:

[[Category: OPOS93_SP]]
[[Category: FPGA]]

{{Under_Construction}}

[[Using_FPGA| << FPGA general page]]

OPOS6UL SP Interfaces description

2025-04-10T06:09:00Z

FabienM: /* Links */

[[Category: OPOS6UL_SP]]
[[Category: FPGA]]
[[Category: Spartan6]]
[[Category: ISE]]
[[Category: XILINX]]

== Introduction ==

This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named '''EIM''' for '''E'''xternal '''I'''nterface '''M'''odule. All description of this bus can be found under the i.MX6UL(L) [https://www.nxp.com/webapp/Download?colCode=IMX6ULRM reference manual] in chapter 21 (page 821).

FPGA used on board is an '''XC6SLX9-2CSG225'''.

== Simplified view ==

[[File:OPOS6UL_SP_EIM_FPGA_INTERFACE.png|600px|center|thumb|'''figure 1''' - ''i.MX6UL(L)-Spartan6 bus description'']]

Normal communication between i.MX6UL(L) processor and Spartan6 fpga is done with black following signals :

* '''EIM_BCLK''' : Clock
* '''EIM_DA[15:0]''': 16bits data and address bus
* '''EIM_LBA (ADV)''': Signal used for data/address muxing
* '''EIM_RW''': Read/Write control signal
* '''EIM_CS0''': Chip select

Gray following signals can be used by EIM (External Interface Memory), but not used in default configuration :

* '''EIM_EB0''': Select byte 0 on bus
* '''EIM_EB1''': Select byte 1 on bus
* '''OE''' : Output enable
* '''EIM_CLK0''': second clock (EIM_ACLK)

Blue following signals are used for FPGA configuration from imx. Some EIM (black) signals are also used for it.

* '''FPGA_INITB''': Initialize FPGA
* '''FPGA_PROGRAM''' : Program (configure) FPGA
* '''FPGA_DONE''': FPGA configuration is done.

== Tutorials ==

* [[opos6ul_sp_fpga_simple_howto | Simple tutorial to make communication]]
== Default configuration on CSx ==

=== Clocks ===

The clock used to clock the FPGA is EIM_BCLK (IO_L1P_CCLK_2(N12) and IO_L29P_GCLK3_2(N8)) and is configured to '''99 MHz'''.

=== Chip Select ===

The EIM memory space is mapped into 128 MB total memory space in the processor
memory. This memory space begin at address '''0x50000000'''.

{| class="wikitable"
! scope="col"| Start address
! scope="col"| End address
! scope="col"| Size
! scope="col"| Name
|-
! scope="row"| 0x5000_0000
| 0x57FF_FFFF
| 128 MB
| EIM (NOR/SRAM)
|}

The total 128 MB of memory can be divided among the EIM four chip selects. See reference manual of i.MX6ULL for more information.

=== Timings ===

==== Read ====

* U-Boot: To read one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
BIOS> md.w 50000000 1
</pre>

* Linux: To read one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
# devmem 0x50000000 16
</pre>
* Bus timings are following :

<wavedrom>
{ signal: [
{ name: "BCLK", wave: "P......" },
{ name: "DA", wave: "x34...x", data: "addr data", node:"..c...d." },
{ name: "ADV", wave: "101...."},
{ name: "RW", wave: "0......"},
{ name: "CS0", wave: "1.0...1"},
{ node:"..a...b." }
],
edge: ['a<-|->b RWSC=4', 'c-a', 'd-b']
}
</wavedrom>

==== Write ====

* U-Boot: To write one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
BIOS> mw.w 50000000 CAFE
</pre>

* Linux: To write one 16 bits value in 0 (0x50000000 in i.MX) do :
<pre class="apf">
# devmem 0x50000000 16 0xCAFE
</pre>
* Bus timings are following :

<wavedrom>
{ signal: [
{ name: "BCLK", wave: "P......" },
{ name: "DA", wave: "x34...x", data: "addr data", node:"..c...d." },
{ name: "ADV", wave: "101...."},
{ name: "RW", wave: "0.1...0"},
{ name: "CS0", wave: "1.0...1"},
{ node:"..a...b." }
],
edge: ['a<-|->b WWSC=4', 'c-a', 'd-b']
}
</wavedrom>

== code & mapping ==
=== Pinout ===

Schematics interfaces is given here :

[[File:Opos6ul_sp_sch_int.jpg]]

UCF example for interface generated by [https://github.com/Martoni/periphondemand POD] is given here :

<pre>
NET "rstgen_syscon00_ext_clk" LOC="N8" | IOSTANDARD=LVCMOS33; # EIM_BCLK
NET "rstgen_syscon00_ext_clk" TNM_NET = "rstgen_syscon00_ext_clk";
TIMESPEC "TS_rstgen_syscon00_ext_clk" = PERIOD "rstgen_syscon00_ext_clk" 10.101 ns HIGH 50 %;
NET "imx6ul_wb16_wrapper00_imx_da<0>" LOC="P11" | IOSTANDARD=LVCMOS33; # EIM_DA0
NET "imx6ul_wb16_wrapper00_imx_cs_n" LOC="R11" | IOSTANDARD=LVCMOS33; # EIM_CS0
NET "imx6ul_wb16_wrapper00_imx_da<1>" LOC="M11" | IOSTANDARD=LVCMOS33; # EIM_DA1
NET "imx6ul_wb16_wrapper00_imx_da<2>" LOC="N11" | IOSTANDARD=LVCMOS33; # EIM_DA2
NET "imx6ul_wb16_wrapper00_imx_da<10>" LOC="R10" | IOSTANDARD=LVCMOS33; # EIM_DA10
NET "imx6ul_wb16_wrapper00_imx_da<11>" LOC="L9" | IOSTANDARD=LVCMOS33; # EIM_DA11
NET "imx6ul_wb16_wrapper00_imx_da<12>" LOC="M10" | IOSTANDARD=LVCMOS33; # EIM_DA12
NET "imx6ul_wb16_wrapper00_imx_da<13>" LOC="M8" | IOSTANDARD=LVCMOS33; # EIM_DA13
NET "imx6ul_wb16_wrapper00_imx_da<14>" LOC="K8" | IOSTANDARD=LVCMOS33; # EIM_DA14
NET "imx6ul_wb16_wrapper00_imx_da<15>" LOC="L8" | IOSTANDARD=LVCMOS33; # EIM_DA15
NET "imx6ul_wb16_wrapper00_imx_adv" LOC="R7" | IOSTANDARD=LVCMOS33; # EIM_LBA
NET "imx6ul_wb16_wrapper00_imx_da<7>" LOC="N6" | IOSTANDARD=LVCMOS33; # EIM_DA7
NET "imx6ul_wb16_wrapper00_imx_rw" LOC="R6" | IOSTANDARD=LVCMOS33; # EIM_RW
NET "imx6ul_wb16_wrapper00_imx_da<3>" LOC="P5" | IOSTANDARD=LVCMOS33; # EIM_DA3
NET "imx6ul_wb16_wrapper00_imx_da<4>" LOC="R5" | IOSTANDARD=LVCMOS33; # EIM_DA4
NET "imx6ul_wb16_wrapper00_imx_da<5>" LOC="L6" | IOSTANDARD=LVCMOS33; # EIM_DA5
NET "imx6ul_wb16_wrapper00_imx_da<6>" LOC="L5" | IOSTANDARD=LVCMOS33; # EIM_DA6
NET "imx6ul_wb16_wrapper00_imx_da<8>" LOC="M5" | IOSTANDARD=LVCMOS33; # EIM_DA8
NET "imx6ul_wb16_wrapper00_imx_da<9>" LOC="N5" | IOSTANDARD=LVCMOS33; # EIM_DA9
NET "irq_mngr00_gls_irq" LOC="P3" | IOSTANDARD=LVCMOS33; # FPGA_INITB
</pre>

=== Simulation model ===

Some simulation model has been written to test eim in VHDL and in python with cocotb.

==== VHDL ====

imx_read and imx_write simulation fonctions are included in POD (Peripheral On Demand) library. Available in [https://github.com/Martoni/pod_lib/blob/master/platforms/opos6ulsp/simulation/opos6ul_test_pkg.vhd platform/opos6ulsp] directory.

==== Cocotb ====

It's possible to simulate eim access with [https://cocotb.readthedocs.io/en/latest/introduction.html cocotb] module named [https://github.com/Martoni/cocotbext-imxeim cocotbext-imxeim].

=== HDL bus wrapper ===

Bus wrapper has been written in VHDL and chisel to convert EIM protocol to Wishbone bus protocol.

==== VHDL ====

A 16 bits multiplexed EIM to 16bits wishbone master bus is available in [https://github.com/Martoni/periphondemand POD] library. The VHDL sources are available following [https://github.com/Martoni/pod_lib/blob/master/library/wrappers/imx6ul_wb16_wrapper/hdl/imx6ul_wb16_wrapper.vhd this link].

==== Chisel ====

A chisel package is available in module [https://github.com/Martoni/ChisArmadeus chisArmadeus] to drive Wishbone master bus with EIM bus [https://github.com/Martoni/ChisArmadeus/blob/master/src/main/scala/chisarmadeus/op6sp/op6sp.scala here].

=== FPGA Interrupt ===

To generate an IRQ from the FPGA to the i.MX, the pin FPGA_INITB is used by default. It correspond to [[GPIOlib#Datasheet_GPIO_number_correspondance | GPIO4_IO16]] on i.MX.

=== FPGA J2 connector mapping ===

Mapping of FPGA pin is given in following [[op6spJ2pinout | csv file]].

== FPGA configuration protocol ==

<TODO>

== Links ==

* [https://www.nxp.com/docs/en/reference-manual/IMX6ULLRM.pdf i.MX6UL(L) reference manual] (PDF chapter 21 page 821)
* [https://www.nxp.com/docs/en/data-sheet/IMX6ULLIEC.pdf i.MX6UL(L) Datasheet] (PDF)
* [https://www.xilinx.com/support/documentation/user_guides/ug380.pdf Spartan6 configuration] (PDF)
* [https://github.com/Martoni/pod_lib/tree/master/platforms/opos6ulsp Peripheral On Demand configuration files]

[[Using_FPGA| << FPGA general page]]

OPOS93 SP Interfaces description

2025-04-10T06:08:40Z

FabienM: Created page with "Category: OPOS93_SP Category: FPGA {{Under_Construction}}"

[[Category: OPOS93_SP]]
[[Category: FPGA]]

{{Under_Construction}}

Using FPGA

2025-04-09T13:23:08Z

FabienM: /* Developing on the APF FPGA */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP''': [[OPOS93_SP Interfaces description]]

| width="50%" |

===Using Armadeus FPGA===
Manage the FPGA from Armadeus distribution.

* Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]].
* Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]]
* [[FPGA_register | Access the FPGA address domain from Linux]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Make some examples ===

These examples give the basis to make VHDL design for FPGA.

* [[Simple blinking LED | LED]]
* [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

Using FPGA

2025-04-09T13:16:48Z

FabienM: /* FPGA Interfaces */

[[Category: FPGA]]
__NOTOC__

==Developing on the APF FPGA==

{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== FPGA Interfaces ===

* '''APF9328''': [[IMX9328-Spartan3 interface description]]
* '''APF27''': [[IMX27-Spartan3A interface description]]
* '''APF51''': [[IMX51-Spartan6 interface description]]
* '''APF6_SP''': [[APF6_SP Interfaces description]]
* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
* '''OPOS93_SP'': [[OPOS93_SP Interfaces description]]

| width="50%" |

===Using Armadeus FPGA===
Manage the FPGA from Armadeus distribution.

* Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]].
* Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]]
* [[FPGA_register | Access the FPGA address domain from Linux]]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
| width="50%" |

=== Make some examples ===

These examples give the basis to make VHDL design for FPGA.

* [[Simple blinking LED | LED]]
* [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]

| width="50%" |

=== Design Tools===
Description of tools used to simulate, to synthesize, and to download/configure FGPA.

'''Xilinx'''
* [[ISE WebPack and Vivado]]

'''Altera'''
* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

'''Lattice'''

* [[IceCube | Install IceCube]]
* [[Diamond | Install Lattice Diamond]]

'''Microsemi'''
* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

=== Automatize FPGA design making ===

==== [[Peripherals On Demand]] ====
For complex projects, POD should be used to simplify design.

==== [[FuseSoC]] ====
FuseSoC is a builder written in Python used to automatize FPGA constructions

==== CactusII ====

[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

| width="50%" |

=== HDL ===

===VHDL ===

* [[VHDL coding styles|VHDL coding styles & externals documentations]]
* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
* [http://www.opencores.org www.opencores.org]
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]

=== Verilog ===

* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification

=== Synthesizable Synchronous HDL ===
==== [[Migen]] ====

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

==== [[Chisel]] ====
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

==== [[SpinalHDL]] ====

[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.

|----------------
|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"

| width="50%" |

===Links===
Some useful links.

''' Wishbone '''
* [http://cdn.opencores.org/downloads/wbspec_b3.pdf official Wishbone specifications]
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]

''' Spartan '''
* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]

''' CycloneV'''
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]

''' OpenSource '''

* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]

| width="50%" |

|}

Armadeus 3

2022-06-30T12:12:18Z

FabienM: /* How-to obtain the Armadeus 3 */

This page will help you use the Armadeus 3.x software release. It also provides you with information about changes compared to the previous 2.x versions of Armadeus.

==Introduction==

Armadeus 3 adds many new features, including the following:

*Some architectural changes to support different hardware targets: [[APF9328]] and [[APF27]]
*New versions of U-Boot (1.3.4), Linux kernel (2.6.27), GCC (4.2.1), Busybox (1.12.1) and also a recent version of Buildroot
*New naming convention of files
*New Flash partition mapping on the target
*TBC

==Important Information regarding documentation==

{{Note|With the introduction of the Armadeus 3 SDK, the Wiki documentation has moved to support the new software. Nevertheless you can download the following HTML dump to have the Armadeus 2.x compatible documentation: [http://www.armadeus.com/assos_downloads/wiki/wiki_assoc_html_dump_03_12_2008.tar.gz Armadeus 2.x wiki]. Wiki will also moved in the next weeks so to have an always Armadeus 3.x compatible HTML dump [http://www.armadeus.com/assos_downloads/wiki/wiki_assoc_html_dump_02_03_2009.tar.gz it's here]
}}

To summarize the documentation changes, here are the rules to adapt the documentation according to your target and version of Armadeus.
* First Armadeus configuration once you have downloaded the Armadeus package found somewhere in First Setup pages:
: Armadeus 3 first command to use according to your <board> (apf9328 or apf27): make <board>_defconfig
: Armadeus 2 first command for apf9328: make

* Binary files location according to your <board> (apf9328 or apf27):
: Armadeus 3 is buildroot/binaries/<board>/
: Armadeus 2 was buildroot/armadeus/

* Armadeus 3 binary files naming convention according to your <board> (apf9328 or apf27):
: <board>-u-boot.brec
: <board>-u-boot.bin
: <board>-linux.bin
: <board>-rootfs.arm.jffs2
: <board>-rootfs.arm.tar

* Armadeus 2 binary files naming convention for apf9328 only:
: u-boot.brec
: u-boot.bin
: linux-kernel-2.6.xx.x-arm.bin
: rootfs.arm.jffs2
: rootfs.arm.tar

* Non configurable users-space tools including compiler for your board (apf9328 or apf27):
: Armadeus 3 tools for the apf9328 are located at buildroot/build_armv4t/
: Armadeus 3 tools for the apf27 are located at buildroot/build_armv5te/
: Armadeus 2 tools are located at buildroot/build_arm/

* Configurable user-space tools (Linux, rootfs, U-Boot, Busybox...) for your board (apf9328 or apf27):
: Armadeus 3 tools for the apf9328 are located at buildroot/project_build_armv4t/apf9328/
: Armadeus 3 tools for the apf27 are located at buildroot/project_build_armv5te/apf27/
: Armadeus 2 tools are located at buildroot/project_build_arm/armadeus/

* cross compilation toolchain for your board (apf9328 or apf27):
: Armadeus 3 source toolchain for the apf9328 is located at buildroot/toolchain_build_armv4t/
: Armadeus 3 source toolchain for the apf27 is located at buildroot/toolchain_build_armv5te/
: Armadeus 2 toolchain is located at buildroot/toolchain_build_arm/

Keeping these rules in mind, you are ready to use any wiki page as a guideline whatever you are working with: Armadeus 2.x or 3.

==How-to obtain the Armadeus 3==

The third generation of Armadeus is either available on the gitlab repository: https://gitlab.com/armadeus/armadeus-bsp/-/tags/release-3.4 or by download: https://gitlab.com/armadeus/armadeus-bsp/-/archive/release-3.4/armadeus-bsp-release-3.4.tar.gz

You can checkout the new version of armadeus or update your working version of armadeus. '''We strongly suggest you to checkout the new version of Armadeus because the new naming convention of files will produce a second directory structure of toolchain, projects, build and image files that could be a source of confusion.'''

* Checkout the new version:

<pre class="host">
git clone git@gitlab.com:armadeus/armadeus-bsp.git armadeus
</pre>

this commmand will download the latest version of Armadeus.

'''Remarks''': '''Do not use spaces''' in the directory name !

* Update your working version of armadeus

'''WARNING: Do not use a simple "git checkout" because some legacy buildroot patches will break your compilation!'''

<pre class="host">
cd armadeus
rm -rf buildroot/package
rm -rf buildroot/target
rm -rf buildroot/toolchain
git checkout -f
make apf9328_defconfig or make apf27_defconfig
</pre>

'''WARNING: the latest command (make <board>_defconfig ) is very important to start with an up to date configuration!'''

At any time you can cleanup the old directories built with armadeus 2:

<pre class="host">
rm -rf buildroot/binaries/armadeus
rm -rf buildroot/build_arm
rm -rf buildroot/project_build_arm
rm -rf buildroot/toolchain_build_arm
</pre>

* How-to obtain the legacy Armadeus 2 (If you're not ready to upgrade your target): Download tar.gz at https://gitlab.com/armadeus/armadeus-bsp/-/tags/release-2.x

==How-to configure and build Armadeus 3==

* After changing the directory to ''armadeus'', you have to configure Armadeus software for the APF target.

<pre class="host">
cd armadeus/
make '''apf9328_defconfig''' or make '''apf27_defconfig'''
</pre>

The '<board>_defconfig' configuration option is the first difference with the previous releases of Armadeus.
This configuration has to be done only once after a checkout or after an update from an older version Armadeus. This command configures Armadeus for the apf board then launches the regular Buildroot configuration menu:

[[Image:Menuconfig3.png]] 

* Configure Armadeus

In System configuration ---> Armadeus Device Support menu, you can check and change the quantity of RAM available on your Armadeus board. (Default value 16MB is just fine with all APF9328 boards and 64MB for the smallest apf27).

In Filesystem images --> for each type of filesystems to build you have the option to copy the binary file to secondary location like your tftp server folder (for exemple /tftpboot).

In Bootloaders --> You will find U-Boot options at the end of this menu including the option to copy U-Boot to a secondary location like /tftpboot

In Kernel --> Destination for linux kernel binaries --> You will find options to copy linux to a secondary location like /tftpboot

* Exit the configuration tool and save your configuration

* Launch the build process and enjoy a cup of coffee for the next hour

<pre class="host">
make
</pre>

The toolchain is built automatically. During this procedure, several files are downloaded from Internet. Please wait for a while.... it takes at least one hour to compile everything! 

* Enjoy the result

The generated binary files can be found in the new subdirectory ''buildroot/binaries/<board>/'':

: '''apf9328-u-boot.brec''' (apf9328 BRecord image that can be used with the bootstrap, if U-Boot is not installed or not working, see [[BootLoader]] page)
: '''<board>-u-boot.bin''' (U-Boot image file to be used with U-Boot itself, see [[BootLoader#Update_U-Boot | updating U-Boot]])
: '''<board>-linux.bin''' (Linux image to use with U-Boot, see [[Target_Software_Installation#Linux_kernel_installation | InstallLinux]])
: '''<board>-rootfs.arm.jffs2''' (FileSystem/RootFS image to use with U-Boot, see [[Target_Software_Installation#Linux_rootfs_installation | RootFS flashing]])
: '''<board>-rootfs.arm.tar''' (for an NFS/MMC RootFS, see [[Network_Configuration#Boot_from_NFS|Booting from NFS]] & [[MultiMediaCard#Booting_from_MMC.2FSD | Booting from a MMC/SD]])

 Please note the new naming convention of binary files and directories

The toolchain and project files share a new nameing convention too:
: '''buildroot/build_armv<x>t''' (contains all non configurable user-space tools)
: '''buildroot/project_build_armv<x>t/<board>''' (contains all configurable user-space tools: target filesystem, linux, busybox and u-boot...)
: '''buildroot/toolchain_build_armv<x>t''' (cross compilation toolchain)

More information is available in the [http://buildroot.uclibc.org/buildroot.html buildroot documentation]

* Prepare binary images for download

The simplest method to prepare binary files for a download to target is to copy them in the tftpboot public directory (for example /tftpboot). You can do it manually:

<pre class="host">
cp -f buildroot/binaries/<board>/* /tftpboot
</pre>

Or you can configure buildroot to copy the image files automatically as described hereabove in '''Configure Armadeus'''. 
From here we will suppose all the image files are available at the root of your tftp server

==How-to upgrade the apf9328 target==

To prepare the upgrade of the target you have to copy binary files from ''buildroot/binaries/apf9328/'' to your ''/tftpboot'' folder or make this process automatic using the command: '''make menuconfig'''. The communication with target is fully compatible with previous versions of Armadeus, as explained in [[Communicate| communicate with the target]]

===update U-Boot (on the target)===

Using the command '''printenv''' check the target IP variables:
BIOS> printenv
bootcmd=run jffsboot
bootdelay=20
...
gatewayip=192.168.0.1
netmask=255.255.255.0
ipaddr=192.168.0.10
serverip=192.168.0.2

'''ipaddr''' is the target IP address and '''serverip''' is the one of the Host PC running the tftp server. The page [[Target_Software_Installation]] will help you to set these variables.

If everything is fine you should be ready to download the new release of u-boot:

* '''Load the new U-Boot code in RAM'''

You can use the following commands to download U-boot: 
With Ethernet and a TFTP server:

BIOS> tftpboot 08000000 apf9328-u-boot.bin

dm9000 i/o: 0x15c00000, id: 0x90000a46
DM9000: running in 16 bit mode
MAC: 00:1e:ac:00:00:02
operating at 100M full duplex mode
TFTP from server 192.168.0.2; our IP address is 192.168.0.10
Filename 'apf9328-u-boot.bin'.
Load address: 0x8000000
Loading: ##################################
done
Bytes transferred = 173036 (2a3ec hex)

Or with Ethernet and a NFS server:
BIOS> nfs 08000000 ${serverip}:/nfs_path_to_buildroot/binaries/apf9328/apf9328-u-boot.bin
Or with the kermit and a serial line
BIOS> loadb 08000000
<CTRL><ALT GR>\
c
send path_to_buildroot/binaries/apf9328/apf9328-u_boot.bin
c

* '''Test the downloaded version of u-boot'''

BIOS> go 08000000

## Starting application at 0x08000000 ...

U-Boot 1.3.4 (Dec 2 2008 - 18:44:41) apf9328 patch 3.3

I2C: ready
DRAM: 16 MB
Flash: 8 MB
In: serial
Out: serial
Err: serial

Hit any key to stop autoboot: 0
BIOS>

* '''Transfer code from RAM to Flash memory'''

There is a simple U-Boot command/script to do that:
BIOS> run flash_uboot

.. done
Un-Protected 2 sectors

.. done
Erased 2 sectors
Copy to Flash... done
.. done
Protected 2 sectors
Flashing uboot succeed
BIOS>

Advanced informations can be found at the [[BootLoader]] wiki page.

* '''Reset the environment variables and reset the board'''

Note: This is important to support the new flash memory mapping. '''!! You will loose all the variables you had defined before !!'''

BIOS> run flash_reset_env

. done
Un-Protected 1 sectors

. done
Erased 1 sectors
Erasing of flash environment variables done!
BIOS>

And do not forget to reset the board by hardware or software.

BIOS> reset

U-Boot 1.3.4 (Dec 2 2008 - 18:44:41) apf9328 patch 3.3

I2C: ready
DRAM: 16 MB
Flash: 8 MB
...

===update linux and rootfs (on the target)===

* Check and set the IP variables:

BIOS> printenv
bootcmd=run jffsboot
bootdelay=20
...
gatewayip=192.168.0.1
netmask=255.255.255.0
ipaddr=192.168.0.10
serverip=192.168.0.2

'''ipaddr''' is the target IP address and '''serverip''' is the one of the Host PC running the tftp server. The page [[Target_Software_Installation]] will help you to set these variables.

You can use the '''dhcp''' command to automatically configure these variables from your DHCP server. You probably will have to adjust the '''serverip''' variable manually.

BIOS> dhcp
dm9000 i/o: 0x15c00000, id: 0x90000a46
MAC: 00:0e:32:00:00:02
operating at 100M full duplex mode
BOOTP broadcast 1
DHCP client bound to address 192.168.0.10
BIOS> setenv serverip 192.168.0.2
BIOS> saveenv

Do not forget to save your changes in FLASH, to have them available at next power up:
BIOS> saveenv

* Update Linux (still on the target)

Using the new release of U-Boot, it is quite simple to update Linux kernel and rootfs using the news scripts included in the release:

BIOS> run update_kernel

dm9000 i/o: 0x15c00000, id: 0x90000a46
DM9000: running in 16 bit mode
MAC: 00:1e:ac:00:00:02
operating at 100M full duplex mode
TFTP from server 192.168.0.2; our IP address is 192.168.0.10
Filename 'apf9328-linux.bin'.
Load address: 0x8000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
##############################################
done
Bytes transferred = 1564776 (17e068 hex)

................ done
Erased 16 sectors
Copy to Flash... done
Flashing kernel succeed

* Update rootfs (still on the target)

BIOS> run update_rootfs

dm9000 i/o: 0x15c00000, id: 0x90000a46
DM9000: running in 16 bit mode
MAC: 00:1e:ac:00:00:02
operating at 100M full duplex mode
TFTP from server 192.168.0.2; our IP address is 192.168.0.10
Filename 'apf9328-rootfs.arm.jffs2'.
Load address: 0x8000000
Loading: #################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
#################################################################
######################################################
done
Bytes transferred = 3932160 (3c0000 hex)

........................................... done
Erased 43 sectors
Copy to Flash... done
Flashing rootfs succeed
BIOS>

===update your fpga firmware (on the target)===

Please follow the standard procedure [[InstallTargetSoftware#FPGA_firmware_installation | Firmware installation]]

==How-to develop with Armadeus / customize your SDK==

Your new Armadeus 3 is running fine on the target. Now you probably would like to customize the target for your project. 
If you are a Buildroot user, the following instructions should sound familiar.

===How-to add a software package===

Use the command '''make menuconfig'''':
<pre class="host">
$ make menuconfig
</pre>

[[Image:menuconfig_package.png]]

Select your package in the menu "package", save the configuration and compile a new rootfs
<pre class="host">
$ make
</pre>

{{Note|For a given release, not all packages are tested/running. You can consult the list of the working packages [[Buildroot-20081103_integration| here]].}}

On the target, download and flash the new rootfs:
<pre class="apf">
BIOS> run update_rootfs
...
BIOS> boot
</pre>

===How-to remove a package===

Supposing you would like to remove an unwanted package from the target.
* The first step is to use the command '''make menuconfig''' to unselect this package but this command will not remove the package from the rootfs. You have to use the ''clean'' command of buildroot. In the lines hereafter replace the word <package> with the real name of your package.
<pre class="host">
$ make menuconfig
... deselect your <package>
$ make <package>-clean
$ make
</pre>
Your new rootfs is now ready to use - Enjoy

* Some packages do not support any uninstall behavior. In such a case you can rebuild your environment using the global clean command. This command requests to compile almost everything and therefore will take time.
<pre class="host">
$ make menuconfig
... deselect your <package>
$ make clean
$ make
</pre>

{{Warning|Using this method you will lose any modification you could have done directly in the directory buildroot/project_build_armvYY/apfXX/root.
Please read the chapter [[Armadeus_3#How-to_modify_root_filesystem| How-to modify root filesystem]] hereafter.}}

Your new rootfs is ready to use - Enjoy

* A faster method exists to force to rebuild rootfs. You can delete the root directory. Unfortunately some libraries (ie c++ lib) are not reinstalled using this method.
<pre class="host">
$ make menuconfig
... deselect your <package>
$ rm -rf buildroot/project_build_armv4t/apf9328/root
$ rm -rf buildroot/project_build_armv4t/apf9328/.root
$ make
</pre>

{{Warning|Using this method you will lose any modification you could have done directly in the directory buildroot/project_build_armvYY/apfXX/root.
Please read the chapter [[Armadeus_3#How-to_modify_root_filesystem| How-to modify root filesystem]] hereafter.}}

Your new rootfs is ready to use - Enjoy

===How-to modify a software===

You would like to modify a package and test your modification on the target. The command '''make <package>-clean''' will force to rebuild the package you modified:
<pre class="host">
$ make <package>-clean
$ make
</pre>
Your new rootfs is ready to use - Enjoy

===How-to create a buildroot package===

The creation of a new buildroot package is described more in depth in the specific wiki page [[Buildroot_Packages]] and in the [http://buildroot.uclibc.org/buildroot.html buildroot documentation]

===How-to modify root filesystem===

There are different methods to modify the rootfs of the apf9328:
# modify files directly on the target (ideal solution for first trials)
# modify files in buildroot/project_build_armv4t/apf9328/root/ (to validate your modification with armadeus)
# modify files in buildroot/target/device/aramdeus/rootfs/target_skeleton (your modifcation will support a '''make clean''' )
# create a patch file in armadeus/patches (your modification will support a '''git checkout''')

===How-to modify Linux kernel===

To rebuild the kernel or any kernel driver you can use the commands:
<pre class="host">
$ make linux-clean
$ make
</pre>

your new Linux kernel and rootfs containing drivers are ready to use - Enjoy

There is another method to rebuild the kernel faster than the previous one:
<pre class="host">
$ make linux
$ make
</pre>
With this method only the modified files are compiled.

===How-to configure a Linux kernel===

There is a command to modify the linux kernel configuration:
<pre class="host">
$make linux-menuconfig
</pre>
Modify your kernel configuration, save your change and rebuild Armadeus in few seconds:
<pre class="host">
$make
</pre>

===How-to configure U-Boot===

you can change the U-Boot configuration using the buildroot command '''make menuconfig'''. U-Boot options are in the sub-menu '''target filesystem options'''. In order to rebuild U-Boot with new options it is necessary to remove U-Boot first:
<pre class="host">
$make menuconfig
...
$make u-boot-dirclean
$make
</pre>

{{Warning| the command '''make u-boot-dirclean''' delete the U-Boot directory and any modification you did in this directory.}}

===How-to modify U-Boot===

To rebuild U-Boot you can use the command '''make u-boot-clean; make'''.
<pre class="host">
$ make u-boot-clean
$ make
</pre>
your new U-Boot is ready to use - Enjoy

If you modify the config file ''apf9328.h'' located in ''buildroot/project_build_armv4t/apf9328/u-boot-1.3.4/include/configs/apf9328.h'', then we suggest you to rebuild the whole u-boot package:
<pre class="host">
$ make u-boot-distclean
$ make
</pre>

===How-to configure busybox===
It also possible to modify the Busybox configuration to add or remove some features:
<pre class="host">
$make busybox-menuconfig
</pre>

To be continued...

==Links==
* [http://buildroot.uclibc.org/buildroot.html Buildroot's documentation]

[[Category:Software]]

Template:ArmadeusNews

2022-06-30T12:06:56Z

FabienM: Undo revision 15106 by FabienM (talk)

__NOTOC__

=====June 30th, 2022: Gitlab is now official repository for armadeus bsp =====
<noinclude>
Gitlab is now official repository for armadeus bsp : https://gitlab.com/armadeus/armadeus-bsp
</noinclude>

=====August 7th, 2018: New software release [[Releases#Release_7.0_.28latest_stable_one.29|Armadeus 7.0]]=====
<noinclude>
This new [[Releases#Release_7.0_.28latest_stable_one.29| release]] introduces the support for the new [[OPOS6UL]] & [[OPOS6UL_NANO]] SoM and concludes the move to Buildroot 2017.02.</noinclude>

=====August 11th, 2015: New software release [[Releases#Release_6.0_.28latest_stable_one.29|Armadeus 6.0]]=====
<noinclude>
This new [[Releases#Release_6.0_.28latest_stable_one.29| release]] introduces the support for the new [[APF6]] & [[APF6_SP]] Armadeus modules and concludes the move to Buildroot 2015.02 and U-Boot 2014.07+. It also consolidates the support for vanilla Linux kernels (3.19+).</noinclude>

=====June 17th, 2014: Bump to [[U-Boot-2014.04| U-Boot 2014.04]]=====
<noinclude>
All Armadeus boards moved to [[U-Boot-2014.04| U-Boot 2014.04]] on [[http://sourceforge.net/p/armadeus/code/ci/master/tree/ GIT]] </noinclude>

<noinclude>
=====December 25th 2013: New software release [[Releases#Release_5.3_.28latest_stable_one.29|Armadeus 5.3]]=====
This new [[Releases#Release_5.3_.28latest_stable_one.29| release]] concludes the move to Buildroot 2013.05 and U-Boot 2013.04. It also consolidates the support for vanilla Linux kernels (3.1x).</noinclude>

<noinclude>
=====June 11th 2013: Bump to Buildroot 2013.05 on GIT [[Current_Buildroot_status_in_Armadeus]]=====
Armadeus moved to Buildroot 2013.05 on GIT. Buildroot 2013.05 will apply after the BSP is fully rebuilt, so first backup your work in progress then do: git pull; git clean -dfx; make apfxx_defconfig; make </noinclude>

<noinclude>
=====October 12th 2012: New software release [[Releases#Release_5.2_.28latest_stable_one.29|Armadeus 5.2]]=====
This new [[Releases#Release_5.2_.28latest_stable_one.29| release]] enhances the supported features on the [[APF28]] board, fix a wireless issue on the PPS board and add few other improvements to the Armadeus software</noinclude>

<noinclude>
=====August 12th 2012: Armadeus 5.0 is released=====
Consolidated support for the [[APF28]] board, BR 2012.02, U-Boot 2012.04, misc. fixes.</noinclude>

<noinclude>
=====January 27th 2012: Armadeus 4.1 is released=====
This new release adds (very preliminary & experimental) support for the [[APF28]] board, BR 2011.05, better BR integration, Linux 3.0 for APF51 and industrial automation new packages.</noinclude>

<noinclude>
=====Some members of Armadeus Project team will attend booth n°71 at LSM 2011 in Strasbourg (11 to 14th July 2011)=====
</noinclude>

<noinclude>
=====July 9th 2011: Armadeus 4.0 is released=====
This new release adds support for the [[APF51]] board, BR 2010.11 and continue integration work (experimental) of Linux 2.6.38 for APF27/PPS & APF9328.</noinclude>

<noinclude>
=====May 1rst 2011: [[APF51]] SOM and [[APF51Dev]] docking board are available=====
These new powerfull boards are available on the Armadeus Systems Online Shop.</noinclude>

<noinclude>
=====March 3rd 2011: [[Release_3.4|Armadeus 3.4]] is released=====
This new release adds support for the [[APF27_PPS]] board, and continue integration work (experimental) of BR 2010.xx & Linux 2.6.38.</noinclude>

<noinclude>
=====July 30th 2010: [[Release_3.3|Armadeus 3.3]] is released=====
This new release adds better support for the [[Wireless_extension_board|APW]], WiFi, Bluetooth, GPS, Qt 4.5.3, BR 2010.05 & U-Boot 2010.03 (experimental), etc... </noinclude>

<noinclude>
=====January 15th 2010: [[Wireless_extension_board|APW]] board is available=====
The new [[Wireless_extension_board|APW]] board ("Wireless" extension for the APF27) is available on the Armadeus Systems Online Shop.</noinclude>

<noinclude>
=====December 1rst 2009: [[Release_3.2|Armadeus 3.2]] is released=====
This new release adds better support for the [[APF27]] & 7" screen, new packages (pygame, xenomai, etc...), svn to git migration, etc... </noinclude>

<noinclude>
=====July 8th 2009: [[Current_events#General_Assembly_.2F_LSM_2009 | General Assembly / LSM 2009 ]]=====
On Wednesday July 8th 2009, occurred the General Assembly in Nantes (France) </noinclude>

<noinclude>
=====June 29th 2009: [[Armadeus 3|Armadeus software 3.1]] is released, following the [[APF27Dev|APF27DevFull]] availability=====
The new Armadeus release 3.1 supports Linux kernel 2.6.29, GDB 6.7.1, APF27 FPGA download, HDMI Output of APF27DevFull and much more.
This release can be downloaded as a tarball package from [http://sourceforge.net/project/showfiles.php?group_id=122057 the usual place]</noinclude>

<noinclude>
=====February 26th 2009: [[Armadeus 3|Armadeus software 3.0]] is released, following the [[APF27]] availability=====
The new Armadeus release 3.0 supports the new Armadeus Systems APF27 board, linux kernel 2.6.27, GCC 4.2.1, U-Boot 1.3.4 and much more.
The software released can be downloaded as a tarball package from the usual place:
http://sourceforge.net/projects/armadeus</noinclude>

<noinclude>
=====December 6th 2008: [[Armadeus 3]] software available from subversion repository=====
The third generation of armadeus software is on the track. The documentation is available at [[Armadeus 3]]. For your convenience a copy of the wiki supporting previous version of Armadeus is available for offline browsing at [http://www.armadeus.com/assos_downloads/wiki/wiki_assoc_html_dump_03_12_2008.tar.gz Armadeus 2.x wiki]</noinclude>

<noinclude>
=====20 May 2008: DevFull boards are available=====
DevFull development boards are available and will be soon sold at discount price (for Armadeus Project members) on [http://www.store.armadeus.com/index.php?language=en armadeus systems online shop]</noinclude>

<noinclude>
=====17 Dec. 2007: Armadeus software version 2.2 released!=====
Armadeus release 2.2 adds many new drivers, fixes many bugs, supports the new linux kernel 2.6.23 and a recent version of buildroot.
Armadeus 2.2 can be downloaded as a tarball package from the usual place:
http://sourceforge.net/projects/armadeus

or directly from the Subversion server (SVN):
svn co https://armadeus.svn.sourceforge.net/svnroot/armadeus/tags/release-2.2 armadeus-2.2 </noinclude>

<noinclude>
=====15 Sept. 2007: APF9328 boards have been received & first DevFull prototypes are under test=====
Now all boards are available. DevFull is working well and will be available at the end of year.</noinclude>

<noinclude>
=====10 Jun. 2007: DevLight and LCD_Adapt received, but still waiting for APF9328 :-( !=====
DevLight and LCD_Adapter boards have been received but we are now waiting for new APF9328.

=====26 Mar. 2007: DevLight and LCD_Adapt ordered !=====
A new DevLight order has been placed! Expected delivey date: week 17/18

The LCD_Adapter boards have been ordered too. Expected delivery date: week 18/19</noinclude>

<noinclude>
=====22 Mar. 2007: DevLight boards are out-of-stock !=====
We have no more DevLight boards for the moment. New one have been ordered but will only be available mid-April</noinclude>
<noinclude>
=====09 Feb. 2007: Release v2.0 is out !=====
Software Release 2.0 is (at least ;-) ) available. To download it, go on Sourceforge... Now serious things can begin ! </noinclude>
<noinclude>
=====05 Nov. 2006: APF DevLight boards received=====
New members can now join us easily.</noinclude>
<noinclude>
=====15 Oct. 2006: APF DevLight boards quite ready=====
DevLight boards are in production and will be available end of October.</noinclude>
<noinclude>
=====12 Sept. 2006: APF DevLight boards ordered=====
Nico has placed an order today for 50 APF DevLight boards. They should arrive mid-october. They will allow more people to join this project soon.</noinclude>
<noinclude>
=====10 Sept. 2006: Wiki and Web sites are quite up now=====
250 years (and some months) after the birth of Wolfgang, a new genius has come to earth: the Armadeus project... ;-)
Wiki and web site (http://www.armadeus.com) begin to rock...</noinclude>

[[Template:ArmadeusNews|Show all News]]

Template:ArmadeusNews

2022-06-30T12:06:31Z

FabienM: /* June 30th, 2022: Gitlab is now official repository for armadeus bsp */

__NOTOC__

=====June 30th, 2022: Gitlab is now official repository for armadeus bsp =====

Gitlab is now official repository for armadeus bsp : https://gitlab.com/armadeus/armadeus-bsp

=====August 7th, 2018: New software release [[Releases#Release_7.0_.28latest_stable_one.29|Armadeus 7.0]]=====
<noinclude>
This new [[Releases#Release_7.0_.28latest_stable_one.29| release]] introduces the support for the new [[OPOS6UL]] & [[OPOS6UL_NANO]] SoM and concludes the move to Buildroot 2017.02.</noinclude>

=====August 11th, 2015: New software release [[Releases#Release_6.0_.28latest_stable_one.29|Armadeus 6.0]]=====
<noinclude>
This new [[Releases#Release_6.0_.28latest_stable_one.29| release]] introduces the support for the new [[APF6]] & [[APF6_SP]] Armadeus modules and concludes the move to Buildroot 2015.02 and U-Boot 2014.07+. It also consolidates the support for vanilla Linux kernels (3.19+).</noinclude>

=====June 17th, 2014: Bump to [[U-Boot-2014.04| U-Boot 2014.04]]=====
<noinclude>
All Armadeus boards moved to [[U-Boot-2014.04| U-Boot 2014.04]] on [[http://sourceforge.net/p/armadeus/code/ci/master/tree/ GIT]] </noinclude>

<noinclude>
=====December 25th 2013: New software release [[Releases#Release_5.3_.28latest_stable_one.29|Armadeus 5.3]]=====
This new [[Releases#Release_5.3_.28latest_stable_one.29| release]] concludes the move to Buildroot 2013.05 and U-Boot 2013.04. It also consolidates the support for vanilla Linux kernels (3.1x).</noinclude>

<noinclude>
=====June 11th 2013: Bump to Buildroot 2013.05 on GIT [[Current_Buildroot_status_in_Armadeus]]=====
Armadeus moved to Buildroot 2013.05 on GIT. Buildroot 2013.05 will apply after the BSP is fully rebuilt, so first backup your work in progress then do: git pull; git clean -dfx; make apfxx_defconfig; make </noinclude>

<noinclude>
=====October 12th 2012: New software release [[Releases#Release_5.2_.28latest_stable_one.29|Armadeus 5.2]]=====
This new [[Releases#Release_5.2_.28latest_stable_one.29| release]] enhances the supported features on the [[APF28]] board, fix a wireless issue on the PPS board and add few other improvements to the Armadeus software</noinclude>

<noinclude>
=====August 12th 2012: Armadeus 5.0 is released=====
Consolidated support for the [[APF28]] board, BR 2012.02, U-Boot 2012.04, misc. fixes.</noinclude>

<noinclude>
=====January 27th 2012: Armadeus 4.1 is released=====
This new release adds (very preliminary & experimental) support for the [[APF28]] board, BR 2011.05, better BR integration, Linux 3.0 for APF51 and industrial automation new packages.</noinclude>

<noinclude>
=====Some members of Armadeus Project team will attend booth n°71 at LSM 2011 in Strasbourg (11 to 14th July 2011)=====
</noinclude>

<noinclude>
=====July 9th 2011: Armadeus 4.0 is released=====
This new release adds support for the [[APF51]] board, BR 2010.11 and continue integration work (experimental) of Linux 2.6.38 for APF27/PPS & APF9328.</noinclude>

<noinclude>
=====May 1rst 2011: [[APF51]] SOM and [[APF51Dev]] docking board are available=====
These new powerfull boards are available on the Armadeus Systems Online Shop.</noinclude>

<noinclude>
=====March 3rd 2011: [[Release_3.4|Armadeus 3.4]] is released=====
This new release adds support for the [[APF27_PPS]] board, and continue integration work (experimental) of BR 2010.xx & Linux 2.6.38.</noinclude>

<noinclude>
=====July 30th 2010: [[Release_3.3|Armadeus 3.3]] is released=====
This new release adds better support for the [[Wireless_extension_board|APW]], WiFi, Bluetooth, GPS, Qt 4.5.3, BR 2010.05 & U-Boot 2010.03 (experimental), etc... </noinclude>

<noinclude>
=====January 15th 2010: [[Wireless_extension_board|APW]] board is available=====
The new [[Wireless_extension_board|APW]] board ("Wireless" extension for the APF27) is available on the Armadeus Systems Online Shop.</noinclude>

<noinclude>
=====December 1rst 2009: [[Release_3.2|Armadeus 3.2]] is released=====
This new release adds better support for the [[APF27]] & 7" screen, new packages (pygame, xenomai, etc...), svn to git migration, etc... </noinclude>

<noinclude>
=====July 8th 2009: [[Current_events#General_Assembly_.2F_LSM_2009 | General Assembly / LSM 2009 ]]=====
On Wednesday July 8th 2009, occurred the General Assembly in Nantes (France) </noinclude>

<noinclude>
=====June 29th 2009: [[Armadeus 3|Armadeus software 3.1]] is released, following the [[APF27Dev|APF27DevFull]] availability=====
The new Armadeus release 3.1 supports Linux kernel 2.6.29, GDB 6.7.1, APF27 FPGA download, HDMI Output of APF27DevFull and much more.
This release can be downloaded as a tarball package from [http://sourceforge.net/project/showfiles.php?group_id=122057 the usual place]</noinclude>

<noinclude>
=====February 26th 2009: [[Armadeus 3|Armadeus software 3.0]] is released, following the [[APF27]] availability=====
The new Armadeus release 3.0 supports the new Armadeus Systems APF27 board, linux kernel 2.6.27, GCC 4.2.1, U-Boot 1.3.4 and much more.
The software released can be downloaded as a tarball package from the usual place:
http://sourceforge.net/projects/armadeus</noinclude>

<noinclude>
=====December 6th 2008: [[Armadeus 3]] software available from subversion repository=====
The third generation of armadeus software is on the track. The documentation is available at [[Armadeus 3]]. For your convenience a copy of the wiki supporting previous version of Armadeus is available for offline browsing at [http://www.armadeus.com/assos_downloads/wiki/wiki_assoc_html_dump_03_12_2008.tar.gz Armadeus 2.x wiki]</noinclude>

<noinclude>
=====20 May 2008: DevFull boards are available=====
DevFull development boards are available and will be soon sold at discount price (for Armadeus Project members) on [http://www.store.armadeus.com/index.php?language=en armadeus systems online shop]</noinclude>

<noinclude>
=====17 Dec. 2007: Armadeus software version 2.2 released!=====
Armadeus release 2.2 adds many new drivers, fixes many bugs, supports the new linux kernel 2.6.23 and a recent version of buildroot.
Armadeus 2.2 can be downloaded as a tarball package from the usual place:
http://sourceforge.net/projects/armadeus

or directly from the Subversion server (SVN):
svn co https://armadeus.svn.sourceforge.net/svnroot/armadeus/tags/release-2.2 armadeus-2.2 </noinclude>

<noinclude>
=====15 Sept. 2007: APF9328 boards have been received & first DevFull prototypes are under test=====
Now all boards are available. DevFull is working well and will be available at the end of year.</noinclude>

<noinclude>
=====10 Jun. 2007: DevLight and LCD_Adapt received, but still waiting for APF9328 :-( !=====
DevLight and LCD_Adapter boards have been received but we are now waiting for new APF9328.

=====26 Mar. 2007: DevLight and LCD_Adapt ordered !=====
A new DevLight order has been placed! Expected delivey date: week 17/18

The LCD_Adapter boards have been ordered too. Expected delivery date: week 18/19</noinclude>

<noinclude>
=====22 Mar. 2007: DevLight boards are out-of-stock !=====
We have no more DevLight boards for the moment. New one have been ordered but will only be available mid-April</noinclude>
<noinclude>
=====09 Feb. 2007: Release v2.0 is out !=====
Software Release 2.0 is (at least ;-) ) available. To download it, go on Sourceforge... Now serious things can begin ! </noinclude>
<noinclude>
=====05 Nov. 2006: APF DevLight boards received=====
New members can now join us easily.</noinclude>
<noinclude>
=====15 Oct. 2006: APF DevLight boards quite ready=====
DevLight boards are in production and will be available end of October.</noinclude>
<noinclude>
=====12 Sept. 2006: APF DevLight boards ordered=====
Nico has placed an order today for 50 APF DevLight boards. They should arrive mid-october. They will allow more people to join this project soon.</noinclude>
<noinclude>
=====10 Sept. 2006: Wiki and Web sites are quite up now=====
250 years (and some months) after the birth of Wolfgang, a new genius has come to earth: the Armadeus project... ;-)
Wiki and web site (http://www.armadeus.com) begin to rock...</noinclude>

[[Template:ArmadeusNews|Show all News]]

Template:ArmadeusNews

2022-06-30T12:05:55Z

FabienM:

Footprints

2022-06-30T12:03:42Z

FabienM:

To develop a custom docking board for an APFxx module, a symbol/footprint component is necessary. As Armadeus systems uses Mentor PAD to design their boards then, by default, PAD's footprint/symbol are approved for industrial designs.
Some footprint/symbol are available for others design software, they are marked '''na''' for '''n'''ot '''a'''pproved if no industrial design has been made with these footprint/symbol.

{| border="1" cellpadding="5" cellspacing="0" align="center"
|- style="background:#efefef;" align="center"
! Software >!! rowspan="2" | Mentor PAD !! rowspan="2" | Mentor PAD export !! rowspan="2" | KiCad !! rowspan="2" | Eagle
|- style="background:#efefef;" align="center"
! Module V
|- align="center"
| [[APF9328]] || not available || not available || not available || not available
|- align="center"
|
[[APF27]]
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf27/PAD/mentor_symbol_apf27.c] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf27/PAD/mentor_footprint_apf27.d]
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf27/PAD_export/mentor_export_symbol_apf27.txt] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf27/PAD_export/mentor_export_footprint_apf27.asc]
|| not available
|| not available
|- align="center"
|
[[APF51]]
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf51/PAD/mentor_symbol_apf51.c] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf51/PAD/mentor_footprint_apf51.d]
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf51/PAD_export/mentor_export_symbol_apf51.txt] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf51/PAD_expert/mentor_export_footprint_apf51.asc]
|| not available
|| not available
|- align="center"
| [[APF28]]
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf28/PAD/mentor_symbol_apf28.c] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf28/PAD/mentor_footprint_apf28.d]
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf28/PAD_export/mentor_export_symbol_apf28.txt] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf28/PAD_export/mentor_export_footprint_apf28.asc]
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf28/kicad/kicad_symbol_apf28.lib] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf28/kicad/kicad_symbol_apf28.kicad_mod]
|| not available
|- align="center"
| [[APF6]]
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf6/PAD/apf6.p] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf6/PAD/apf6.d]
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf6/PAD_export/apf6.txt] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/apf6/PAD_export/footprint.asc]
|| not available
|| not available
|- align="center"
| [[APF6_SP]]
|| TODO
|| TODO
|| not available
|| not available
|- align="center"
| [[OPOS6UL]]
|| TODO
|| TODO
|| [https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/opos6ul/kicad/opos6ul.lib)] 
[https://gitlab.com/armadeus/armadeus-bsp/-/tree/master/hardware/opos6ul/kicad/Opos6ul_Socket_SODIMM_DDR3_TE_2013289.kicad_mod]
|| not available
|- align="center"
| [[OPOS6UL_NANO]]
|| TODO
|| TODO
|| TODO
|| not available
|- align="center"
| [[OPOS6UL_SP]]
|| TODO
|| TODO
|| TODO
|| not available
|}

All Symbols/Footprint described in this table can be found in [[Toolchain#Get_Armadeus_software | Armadeus gitlab repository]] in '''hardware''' directory.

APF6 legacy Linux 4.1 kernel status

2022-06-30T11:50:05Z

FabienM:

[[Category: kernel]]
[[Category: APF6]]
The [[APF6]] Linux distribution can be found here: [https://gitlab.com/armadeus/armadeus-bsp/-/tags latest stable installation tarball from gitlab]

==Current version==
Currently (armadeus-6.0) default supported Linux version for APF6 is: '''vanilla 3.19'''. Details about this kernel can be found [[APF6_Linux_kernel_status|here]].

We also support "legacy" kernels, based on Freescale/Wandboard's versions, to have GPU/VPU functionalities available until integrated in vanilla/mainline. This page detail the Freescale 4.1.xxx Linux version support.

Details concerning the drivers usage can be found [[Setup|below]].

* NT = Not Tested
* NA = Not Available / Not possible

==APF6 module==

{| border="1" cellpadding="5" cellspacing="0" summary="Functionnalities test results"
|----------------
| colspan="5" align="center" style="background:#b9e9a3;" | '''4.1.15_2.0.0_ga legacy'''
|- style="background:#efefef;"
! '''Driver''' || colspan="2" | '''Compiling ? Static / Module''' || ''' Working ? ''' || '''Comments'''
|----------------
|'''eMMC''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK ||
|----------------
|'''SPI''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || [[SPI]] / Not tested yet.
|----------------
|'''I2C''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[I2C]]
|----------------
|'''Keypad''' || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || Not tested yet
|----------------
|'''MMC/SD/SDIO''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK ||
|----------------
|'''UART''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK ||
|----------------
|'''Ethernet''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK ||
|----------------
|'''USB OTG''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[USB]]
|----------------
|'''USB HOST1''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[USB]]
|----------------
|'''PWM''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[PWM]]
|----------------
|'''RTC''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || i.MX6 internal [[RTC]]
|----------------
|'''Watchdog''' || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || [[Watchdog]]
|----------------
|'''PM sleep/wakeup''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || [[Power management]]
|----------------
|'''Frequency scaling''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || Not tested yet
|----------------
|'''CSI (Camera)''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || Tested with a wandcam and SDL capture demo.
|----------------
|'''SSI (Audio)''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[ALSA]]
|----------------
|'''Video codec (H.263/4)''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || H.264 with [[Gstreamer]]
|----------------
|'''3D GPU''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || OpenGLES 2.0
|----------------
|'''Security/Sahara/RTIC''' || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || Not tested yet
|----------------
|'''Wi-Fi (b/g)''' || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || [[Wifi]] - [[Wl12xx_driver]]
|----------------
|'''Bluetooth''' || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || [[Bluetooth]] / No RTS/CTS Bluetooth
|----------------
|'''FPGA POD interface''' || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || Not tested yet
|----------------
|'''FPGA loading''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || Only available on APF6SP
|----------------
|'''Xenomai''' || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT
|----------------
|}

==APF6Dev development baseboard==
* NT = Not Tested
* NA = Not Available / Not possible

{| border="1" cellpadding="5" cellspacing="0" summary="Functionnalities test results"
|----------------
| colspan="5" align="center" style="background:#b9e9a3;" | '''4.1.15_2.0.0_ga legacy'''
|- style="background:#efefef;"
! '''Driver''' || colspan="2" | '''Compiling ? Static / Module''' || '''Working ?''' || '''Comments'''
|----------------
|'''SATA''' || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT ||
|----------------
|'''PCIe''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT ||
|----------------
|'''microSD''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK ||
|----------------
|'''Ethernet''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:orange;" | ~OK || 100M only at the moment
|----------------
|'''LCD''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || Tested with LW700. [[LCD]]
|----------------
|'''Backlight''' || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || Not tested yet
|----------------
|'''Headphone audio Out''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[ALSA]]
|----------------
|'''SPDIF Optical audio Out''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[ALSA]] be sure to force SPDIF output with: aplay -D "default:CARD=imxspdif" /usr/share/sounds/alsa/Side_Left.wav
|----------------
|'''HDMI audio Out''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[ALSA]]
|----------------
|'''MIC audio In''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[ALSA]]
|----------------
|'''Touchscreen''' || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || Single touch only.
|----------------
|'''USB Host 1''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || High Speed
|----------------
|'''CAN Bus''' || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || [[CAN_bus_Linux_driver]]
|----------------
|'''HDMI''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || Issues with some DVI monitor.
|----------------
|'''GPS''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || [[GPS]]
|----------------
|'''GSM / 3G''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || [[Gsm]]
|----------------
|'''GPIO''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[GPIOlib]]
|----------------
|'''User LED''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[GPIO LEDS]]
|----------------
|'''User button''' || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || style="background:#00ff00;" | OK || [[GPIO keys]]
|----------------
|'''RTC MCP79400''' || style="background:#00ff00;" | NT || style="background:#00ff00;" | OK || style="background:#eeee00;" | NT || [[RTC]]. Timekeeping only.
|}

APF27 Linux kernel status

2022-06-30T11:49:34Z

FabienM:

See [[Kernel-upstream-status]] for fresh information about APF27 kernel status.

The APF27 Linux distribution can be found here: [https://gitlab.com/armadeus/armadeus-bsp/-/tags latest stable installation tarball from gitlab]

==Current version==
Currently (Armadeus-6.0) supported Linux version is: '''2.6.29.6'''.
Details concerning the drivers usage can be found [[Setup|here]].

* NT = Not Tested
* NA = Not Available / Not possible

==APF27 module (ie i.MX27 internal controllers + FPGA)==

{| border="1" cellpadding="5" cellspacing="0" summary="Functionnalities test results"
|----------------
| colspan="5" align="center" style="background:#b9e9a3;" | '''2.6.29.6'''
|----------------
! '''Driver''' || colspan="2" | '''Compiling ? Static / Module''' || ''' Working ? ''' || '''Comments'''
|----------------
|'''NAND Flash''' || style="background:#00ff00;" | OK || NA || style="background:#00ff00;" |OK ||
|----------------
|'''PCMCIA''' || NA || NA || NA || can not be used on the APF27
|----------------
|'''1Wire''' || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT || not integrated yet
|----------------
|'''ATA''' || NA || NA || NA || can not be used on the APF27
|----------------
|'''SPI''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''I2C''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''Keypad''' || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT || not integrated yet

|----------------
|'''MMC/SD/SDIO''' || style="background:#00ff00;" | OK || NA || style="background:#00ff00;" | OK ||

|----------------
|'''UART''' || style="background:#00ff00;" | OK || NA || style="background:#00ff00;" | OK ||

|----------------
|'''Ethernet''' || style="background:#00ff00;" | OK || NA || style="background:#00ff00;" | OK ||

|----------------
|'''USB OTG''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || Used as High Speed Host only (for the moment == on APF27Dev)

|----------------
|'''USB HOST1''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''USB HOST2''' || NA || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT ||

|----------------
|'''PWM''' || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''RTC''' || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT || internal RTC
|----------------
|'''Watchdog''' || style="background:#eeee00;" |NT || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || i.MX27 internal Watchdog
|----------------
|'''CSI''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''GPIO''' || style="background:#00ff00;" | OK || NA || style="background:#f6b400;" | Partially || GPIOlib work but no interrupts with /sys/class/gpio/gpioX/edge file

|----------------
|'''LCD''' || style="background:#00ff00;" | OK || NA || style="background:#00ff00;" | OK ||

|----------------
|'''SSI (Audio)''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''Video codec (H.263/4)''' || NA || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT || Only encoding was validated. Mostly relies on userspace tools.

|----------------
|'''Security/Sahara/RTIC''' || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT || style="background:#eeee00;" |NT ||

|----------------
|'''FPGA POD interface''' || NA || style="background:#00ff00;" | OK|| style="background:#00ff00;" | OK || Wishbone bus

|----------------
|'''FPGA loading''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|}

==APF27Dev development baseboard==
* NT = Not Tested
* NA = Not Available / Not possible

{| border="1" cellpadding="5" cellspacing="0" summary="Functionnalities test results"
| colspan="5" align="center" style="background:#b9e9a3;" | '''2.6.29.6'''
|- style="background:#efefef;"
! '''Driver''' || colspan="2" | '''Compiling ? Static / Module''' || ''' Working ? ''' || '''Comments'''
|----------------
|'''RTC''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" |OK || [[RTC|DS1374]]

|----------------
|'''microSD''' || NA || style="background:#00ff00;" | OK|| style="background:#00ff00;" | OK ||

|----------------
|'''Ethernet''' || style="background:#00ff00;" | OK || NA || style="background:#00ff00;" | OK ||

|----------------
|'''RS232''' || style="background:#00ff00;" | OK || NA || style="background:#00ff00;" | OK ||

|----------------
|'''LCD''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''Audio out''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || [[ALSA]]
|----------------
|'''Audio in''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''Touchscreen''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || [[TSC2102_Linux_driver]]

|----------------
|'''USB Host High Speed''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''USB Host Full Speed''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK ||

|----------------
|'''ADC''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || MAX1027

|----------------
|'''DAC''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || MAX5821

|----------------
|'''CAN Bus''' || NA || style="background:#eeee00;" |NT|| style="background:#eeee00;" | NT || MCP2515

|----------------
|'''HDMI''' || colspan="2" | No drivers needed || style="background:#00ff00;" | OK || [[DVI_/_HDMI|AD9889]]

|----------------
|'''GPS''' || colspan="2" | No drivers needed || style="background:#00ff00;" | OK || [[Wireless extension board]]

|----------------
|'''GSM''' || colspan="2" | No drivers needed || style="background:#00ff00;" | OK || [[Wireless extension board]]

|----------------
|'''Wi-Fi''' || NA || style="background:#00ff00;" | OK || style="background:#00ff00;" | OK || [[Wireless extension board]]

|----------------
|'''Bluetooth''' || NA || style="background:#eeee00;" | NT || style="background:#eeee00;" | NT || [[Wireless extension board]]

|----------------
|}

[[Category: kernel]]

Quilt

2022-06-30T11:44:44Z

FabienM:

== Introduction ==
Quilt is a little tool used to manage patches. The project is hosted on [http://savannah.nongnu.org/projects/quilt savannah forge] and can be found in debian package repository.

== Using quilt in Armadeus project ==

Quilt is useful when linux kernel or buildroot modification must be done. Because Armadeus use official linux/buildroot sources, each specific modification for our platform must be done with a patch. And patches are versionned on Armadeus gitlab repository in directory buildroot/target/device/armadeus/linux/kernel-patches/ for Linux kernel and in patches/buildroot for buildroot.

=== quiltify.sh ===

To use it under Armadeus Project, a simple script was written to simplify it : ''quiltify.sh''. Launch it from the root project :

<pre class="host">
[ ] $ ./scripts/quiltify.sh
</pre>

Then answer questions (defaults are recommended). For linux kernel, quiltify will rename your source directory and download/patch/compile again the sources.

=== By Hand ===

quiltify is used when patch are stored in Armadeus standard directory. For specific projects, where patches are stored elsewhere it doesn't work. To do this, you can follow this procedure:

* linux-dirclean: linux kernel should be rebuild from ''scratch'' then first we have to cut the branch (in bsp root directory do):
<pre class="host">
$ make linux-dirclean
</pre>
* linux-extract: We have to just extract virgin linux source (don't compile yet):
<pre class="host">
$ make linux-extract
</pre>
* Once extract done, go to linux source directory and add patch one by one :
<pre class="host">
$ cd buildroot/output/build/linux-5.3-rc4/
# Import patches one by one:
$ quilt import /Path/to/personnal/kernel/patches/my_wonderful_patch.patch
# All patches from a directory:
$ quilt import /Path/to/personnal/kernel/patches/*.patch
</pre>

=== Play with quilt ===

Once you done it, you can go to linux sources directory ''buildroot/project_build_armv5te/apf27/linux-2.6.29.6'' then list all patches applied to with quilt command :
<pre class="host">
[ ] $ quilt applied
015-armadeus-logo-add_armadeus-project_tux.patch
016-armadeus-imxfb-add_platform_specific_init_exit_functions.patch
018-armadeus-i2c-imx-add_driver_to_linux_build_system.patch
…
336-armadeus-imxfb-makes_it_compatible_with_arch_imx.patch
337-armadeus-imxfb-add_lcd_clock_def_for_imx_platform.patch
338-denx-mxcgpio-emulates_interrupt_on_both_edges.patch
339-apf27-armadeus-spidev.patch
</pre>

If you want to create a new patch, just use ''new'' quilt command. Then '''before''' modifying Linux file, add it to quilt with ''add'' command.

The file can be modified according to your wish.

Once modification done, you can generate the patch using ''refresh'' command. To add yours patches in the right directory, go to your project root then launch the script with ''export'' command :
<pre class="host">
[ ] $ ./scripts/quiltify.sh export
</pre>

Your patch is now ready to be committed on Armadeus gitlab.

== Documentation ==

The [http://linux.die.net/man/1/quilt man page] of quilt is a good documentation, it's strongly recommended to read it before using it.

How to make a VHDL design in Ubuntu/Debian

2022-06-30T10:44:55Z

FabienM:

[[Category: FPGA]]

This tutorial describes how to install all the necessary tools to develop simple designs under Ubuntu for the Armadeus Project. 
As Ubuntu is a Debian based distribution, all the informations on this page should work with Debian too.

== Editing VHDL ==

To edit VHDL code all standard editing softwares like Vim, Emacs or others can be used.
But Emacs has a really good [http://www.iis.ee.ethz.ch/~zimmi/emacs/vhdl-mode.html vhdl-mode] used by lots of designers. If you hate Emacs, you
can use the xilinx-embedded editor or vim with a [http://code.google.com/p/vim-vhdl/ VHDL-plugin] under development.

== Making a simple project ==

It's a good idea to make a clean project tree for your design, because different software are
used and each generates a large amount of files.

Here is an example of a VHDL project tree :

* '''MySimple_project/'''
**'''src/''' for all sources files (.vhd,.ucf,.xcf)
**'''testbench/''' VHDL sources files for testing your design
**'''ise/''' Xilinx web pack will work in this directory
**'''simu/''' All files generated by the simulator

== Simulation ==
To stay in the Free Software spirit, the best method to simulate is to use [http://ghdl.free.fr/ GHDL] (based on GCC). 
To install it on Ubuntu you just have to type :
$ sudo apt-get install ghdl

You can find a good tutorial for using GHDL [http://forum.ubuntu-fr.org/viewtopic.php?pid=1545563#p839075 here] and on [http://ghdl.free.fr/ghdl/Starting-with-GHDL.html#Starting-with-GHDL the official website]. It's supposed that the project tree
used is this one described previously.

Analysing files:
$ ghdl -i --ieee=synopsys --warn-no-vital-generic --workdir=simu --work=work src/*.vhdl testbench/testb_file.vhd
And compile:
$ ghdl -m --ieee=synopsys --warn-no-vital-generic --workdir=simu --work=work testb_file

After that a binary file named ''testb_file'' is created; to launch simulation we just have to:
$ ./testb_file --stop-time=500ns --vcdgz=testb_file.vcdgz
The stop time option sets the simulation time and the vcdgz option will generate a gunzip compressed wave file to visualize the result.

Visualizing the result can be done with gtkwave:
$ sudo apt-get install gtkwave

We can launch it with the following command :
$ gunzip --stdout testb_file.vcdgz | gtkwave --vcd

[[Image:gtkwave.png|700px]]

It can be a good idea to make a Makefile instead of typing all this commands, here is a little Makefile:

<code lang="makefile">

# project name
PROJECT=bus_led_top
# vhdl files
FILES = src/bus_led.vhd src/bus_led_top.vhd
# testbench
SIMTOP = led_top_tb
SIMFILES = testbench/led_top_tb.vhd
# Simu break condition
GHDL_SIM_OPT = --assert-level=error
#GHDL_SIM_OPT = --stop-time=500ns

SIMDIR = simu
SYNTHFILES = bin/bus_led_ise/netgen/synthesis

GHDL_CMD = ghdl
GHDL_FLAGS = --ieee=synopsys --warn-no-vital-generic

VIEW_CMD = /usr/bin/gtkwave

ghdl-compile :
mkdir -p simu
$(GHDL_CMD) -i $(GHDL_FLAGS) --workdir=simu --work=work $(SIMFILES) $(FILES)
$(GHDL_CMD) -m $(GHDL_FLAGS) --workdir=simu --work=work $(SIMTOP)
@mv $(SIMTOP) simu/$(SIMTOP)

ghdl-run :
@$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz

ghdl-view:
gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd

ghdl-clean :
$(GHDL_CMD) --clean --workdir=simu
</code>

to use it, just write :
$ make ghdl-compile
to compile, then:
$ make ghdl-run
to run the design, then:
$ make ghdl-view
to launch gtkwave and visualize the results.

== Syntesis, place & route ==

=== GUI installation ===
To synthesize the design it is mandatory to use Xilinx tools (It's not exactly true, others tools can be used for synthesize like Mentor tools, but at the end, to make the bitstream, Xilinx tools are mandatory), fortunately Xilinx provides his webpack for Linux. [[ISE_WebPack_installation_on_Linux| Click here if you didn't install it yet.]]

To launch the floorplanner, DISPLAY has to be change:
<pre class="host">
export DISPLAY=:0
</pre>

After this installation, ISE can be found in the directory ''$(Xilinx_root_dir)/bin/lin''.
To avoid retyping export, a little script ''launch_ise.sh'' can be made in ''bin/lin/'' directory:
<source lang="bash">
#!/bin/bash
export DISPLAY=:0
~/Xilinx92i/bin/lin/ise
</source>

Then make launch click :

[[Image:lanceurise.png]]

There is a good tutorial on [http://harded.free.fr/site/?p=31 harded.free.fr].

=== Using Xilinx command line tools for shell syntesis ===

See [http://panteltje.com/panteltje/fpga/index.html Using Xilinx Webpack-8.1i on grml Linux in scripted mode, without GUI] for an introduction.

First of all, library files has to be copied in library directory :
sudo -s
mkdir /usr/local/lib/xilinx/
cp Xilinx_directory/bin/lin/*.so /usr/local/lib/xilinx/
echo /usr/local/lib/xilinx >> /etc/ld.so.conf
ldconfig

Then modify your .bashrc (add at the end):
PLATFORM=lin
XILINX=Xilinx_directory
export XILINX
PATH=Xilinx_directory/bin/lin:$PATH
export PATH

Then ISE can be used in command line (xst, ngdbuild, map, bit,...). To avoid typing very long commands it can be a good idea to use a Makefile, xess.com provide a full [http://www.xess.com/appnotes/makefile.php Makefile] to do this and a basic Makefile for simulation and synthesis can be found in the armadeus gitlab project: [https://gitlab.com/armadeus/armadeus-bsp/-/blob/master/firmware/wishbone_example/wishbone_example9328_27/Makefile]. To use it modify the head and write the names of your files :

*General options

# project name
PROJECT=bus_led_top
# vhdl files
FILES = src/bus_led.vhd src/bus_led_top.vhd

* constraints for synthesis

# pin configuration
UCF_FILE = src/bus_led.ucf
# Synthesis constraints file
XCF_FILE =

*Testbench options

# testbench
SIMTOP = led_top_tb
SIMFILES = ../apf_pkg/apf_test_pkg.vhd testbench/led_top_tb.vhd

*Simulation can stop after a given time or after an assert error (end of test for example)

# Simu break condition
GHDL_SIM_OPT = --assert-level=error
#GHDL_SIM_OPT = --stop-time=500ns